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D.M.H. Walker

Observed names: D. M. H. Walker, D. M. Walker, D.M. Walker, Duncan M. (Hank) Walker, Duncan M. Hank Walker, Duncan M. Walker, Duncan M.H. Walker
ORCID: 0000-0002-4839-3830
Observed ORCID: 0000-0002-4839-3830
OpenAlex ID: A5027337337
K longest paths per gate (KLPG) test generation for scan-based sequential circuits
2004 · W. Qiu, Jing Wang, et al. · IEEE International Test Conference (ITC) · 118
An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit
2004 · Wangqi Qiu, D.M.H. Walker · IEEE International Test Conference (ITC) · 113
Power Supply Noise in Delay Testing
2006 · Jing Wang, D. M. H. Walker, et al. · IEEE International Test Conference (ITC) · 80
Resistive bridge fault modeling, simulation and test generation
2003 · V.R. Sar-Dessai, D.M.H. Walker · IEEE International Test Conference (ITC) · 74
Longest-path selection for delay test under process variation
2005 · Xiang Lu, Zhuo Li, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 53
A circuit level fault model for resistive opens and bridges
2003 · Zhuo Li, Xiang Lu, et al. · IEEE VLSI Test Symposium (VTS) · 51
IDDX-based test methods
2004 · Sagar S. Sabade, Duncan M. Walker · ACM Transactions on Design Automation of Electronic Systems · 45
Longest path selection for delay test under process variation
2004 · X. Lu, Z. Li, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 41
A circuit level fault model for resistive bridges
2003 · Zhuo Li, Xiang Lu, et al. · ACM Transactions on Design Automation of Electronic Systems · 39
FedEx - a fast bridging fault extractor
2002 · Z. Stanojevic, D.M.H. Walker · IEEE International Test Conference (ITC) · 39
Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages
2002 · Yuyun Liao, D.M.H. Walker · IEEE International Test Conference (ITC) · 38
Test generation for global delay faults
2002 · G.M. Luong, D.M.H. Walker · IEEE International Test Conference (ITC) · 38
Improved wafer-level spatial analysis for I/sub DDQ/ limit setting
2002 · S. Sabade, D.M.H. Walker · IEEE International Test Conference (ITC) · 38
A vector-based approach for power supply noise analysis in test compaction
2006 · Jing Wang, Ziding Yue, et al. · IEEE International Test Conference (ITC) · 35
Evaluation of effectiveness of median of absolute deviations outlier rejection-based I/sub DDQ/ testing for burn-in reduction
2003 · S.S. Sabade, D.M. Walker · IEEE VLSI Test Symposium (VTS) · 34
Dynamic Compaction for High Quality Delay Test
2008 · Zheng Wang, D.M.H. Walker · IEEE VLSI Test Symposium (VTS) · 33
A statistical fault coverage metric for realistic path delay faults
2004 · Wangqi Qiu, Xiang Lu, et al. · IEEE VLSI Test Symposium (VTS) · 30
Timing analysis of combinational circuits including capacitive coupling and statistical process variation
2002 · B. Choi, D.M.H. Walker · IEEE VLSI Test Symposium (VTS) · 29
Modeling Power Supply Noise in Delay Testing
2007 · Jing Wang, D.M. Walker, et al. · IEEE Design & Test of Computers · 28
A practical built-in current sensor for I/sub DDQ/ testing
2002 · Hoki Kim, D.M.H. Walker, et al. · IEEE International Test Conference (ITC) · 28
PROBE: a PPSFP simulator for resistive bridging faults
2002 · Chul Young Lee, D.M.H. Walker · IEEE VLSI Test Symposium (VTS) · 28
Accurate fault modeling and fault simulation of resistive bridges
2002 · V. Sar-Dessai, D.M.H. Walker · Proceedings · 26
Yield learning via functional test data
2002 · Young-Jun Kwon, D.M.H. Walker · IEEE International Test Conference (ITC) · 24
I/sub DDQ/ test: will it survive the DSM challenge?
2002 · S.S. Sabade, D.M.H. Walker · IEEE Design & Test of Computers · 24
Power supply noise control in pseudo functional test
2013 · Tengteng Zhang, Duncan M. Hank Walker · IEEE VLSI Test Symposium (VTS) · 22
Works count: 105
Citation count: 1,630
H-index: 24
I10-index: 49
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