Impact of CMOS process scaling and SOI on the soft error rates of logic processes
Year: 2002
Type: conference-paper
Source: Symposium on VLSI Technology
Institution: Intel (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
Funder: Los Alamos National Laboratory
OpenAlex ID: W1960026154