Work

Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface

Year: 2006

Type: conference-paper

Source: IEEE International Conference on Electronics, Circuits and Systems (ICECS)

DOI: 10.1109/icecs.2006.379929

Author: Jan Schat

Institution: Philips (Germany)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W1978268262

FWCI:

Cites: 3

Cited by:

Related to: 10