Work

Crosstalk fault modeling in defective pair of interconnects

Year: 2007

Type: article

Source: Integration

DOI: 10.1016/j.vlsi.2007.04.005

Authors: Ajoy K. Palit, Kishore K. Duganapalli, Walter Anheier

Institution: University of Bremen

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2000725739

FWCI: 4.575

Cites: 8

Cited by: 14

Related to: 10