Work

At-speed capture power reduction using layout-aware granular clock gate enable controls

Year: 2014

Type: conference-paper

Source: IEEE International Test Conference (ITC)

DOI: 10.1109/test.2014.7035296

Authors: R. Shaikh, P. Wilson, K. Agarwal, H. V. Sanjay, R. Tiwari, K. Lath, S. Ravi

Institution: Texas Instruments (India)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2003272148

FWCI: 0.744

Cites: 20

Cited by: 10

Related to: 10