Work

New fault model analysis for embedded SRAM cell for deep submicron technologies using parasitic extraction method

Year: 2015

Type: conference-paper

Source: IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

DOI: 10.1109/vlsi-sata.2015.7050471

Authors: M. Parvathi, N. Vasantha, K. Satya Prasad

Institution: Jawaharlal Nehru Technological University, Kakinada

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2016101289

FWCI: 0.221

Cites: 12

Cited by: 4

Related to: 10