Work

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

Year: 2013

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2013.2272340

Authors: Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt

Institution: Infineon Technologies (Austria)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Karl-Franzens-Universität Graz, Infineon Technologies

OpenAlex ID: W2023401960

FWCI: 3.533

Cites: 12

Cited by: 64

Related to: 10