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Nicola Da Dalt

Observed names: Da Dalt N, N Da Dalt, N. Da Dalt, Nicola da Dalt
OpenAlex ID: A5111819598
A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs
2005 · N. Da Dalt · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 157
On the jitter requirements of the sampling clock for analog-to-digital converters
2002 · N. Da Dalt, M. Harteneck, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 121
Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation
2008 · N. Da Dalt · IEEE Transactions on Circuits and Systems I Regular Papers · 115
Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs
2006 · Nicola Da Dalt · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 102
Understanding Jitter and Phase Noise: A Circuits and Systems Perspective
2018 · Nicola Da Dalt, Ali Sheikholeslami · Cambridge University Press eBooks · 84
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS
2005 · N. Da Dalt, E. Thaller, et al. · IEEE Journal of Solid-State Circuits · 78
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS
2010 · Werner Grollitsch, Roberto Nonis, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 73
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture
2013 · Roberto Nonis, Werner Grollitsch, et al. · IEEE Journal of Solid-State Circuits · 64
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture
2005 · R. Nonis, N. Da Dalt, et al. · IEEE Journal of Solid-State Circuits · 64
An Analysis of Phase Noise in Realigned VCOs
2014 · Nicola Da Dalt · IEEE Transactions on Circuits & Systems II Express Briefs · 40
A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS
2003 · N. Da Dalt, C. Sandner · IEEE Journal of Solid-State Circuits · 39
A 0.06 mm$^{2}$ 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS
2010 · Stefano Dal Toso, Andrea Bevilacqua, et al. · IEEE Journal of Solid-State Circuits · 38
A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS
2006 · N. Da Dalt, C. Knopf, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 37
An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands $S$ Through $K_{u}$
2010 · Stefano Dal Toso, A Bevilacqua, et al. · IEEE Transactions on Microwave Theory and Techniques · 26
Dynamics of induced modulational instability in waveguides with saturable nonlinearity
1995 · N. Da Dalt, C. De Angelis, et al. · Optics Communications · 24
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology
2002 · N. Da Dalt, S. Derksen, et al. · IEEE Journal of Solid-State Circuits · 19
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider
2013 · R. Nonis, W. Grollitsch, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 17
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming
2009 · S. Mendel, C. Vogel, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 17
Efficient Statistical Simulation of Intersymbol Interference and Jitter in High-Speed Serial Interfaces
2013 · Andrea Cristofoli, Pierpaolo Palestri, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 16
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs
2008 · L. Bizjak, N. Da Dalt, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 15
A low jitter triple-band digital LC PLL in 130nm CMOS
2004 · N. Da Dalt, E. Thaller, et al. · European Solid-State Circuits Conference (ESSCIRC) · 12
A fully integrated 13 GHz ΔΣ fractional-n PLL in 0.13 μm CMOS
2004 · M. Tiebout, C. Sandner, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
An all-digital PLL using random modulation for SSC generation in 65nm CMOS
2013 · N. Da Dalt, P. Pridnig, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
Jitter Noise of Sampled Multitone Signals
2011 · Martin Clara, Nicola Da Dalt · IEEE Transactions on Circuits & Systems II Express Briefs · 6
Signal and timing analysis of a phase-domain all-digital phase-locked loop with reference retiming mechanism
2009 · Stefan Mendel, Christian Vogel, et al. · International Conference Mixed Design of Integrated Circuits and Systems · 6
Works count: 62
Citation count: 1,219
H-index: 17
I10-index: 21
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