Work

Cost and benefit models for logic and memory BIST

Year: 2000

Type: conference-paper

Source: Design, Automation, and Test in Europe

DOI: 10.1145/343647.343900

Authors: Juin-Ming Lu, Cheng-Wen Wu

Institution: National Tsing Hua University

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2052075243

FWCI: 0.869

Cites: 15

Cited by: 24

Related to: 10