Work

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Year: 2006

Type: conference-paper

Source: ACM/IEEE Design Automation Conference (DAC)

DOI: 10.1109/dac.2006.229278

Authors: S. Pandey, M. Glesner

Institution: Technische Universität Darmstadt

Language: English

Topic: Interconnection Networks and Systems

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2113837795

FWCI: 2.466

Cites: 27

Cited by: 13

Related to: 10