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Sujan Pandey

Observed names: Pandey, Sujan, S. Pandey
Institution: NXP (Netherlands)
OpenAlex ID: A5000000560
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
2006 · S. Pandey, M. Glesner · ACM/IEEE Design Automation Conference (DAC) · 13
Performance Aware On-Chip Communication Synthesis and Optimization for Shared Multi-Bus Based Architecture
2005 · Sujan Pandey, Manfred Glesner, et al. · Symposium on Integrated Circuits and Systems Design · 11
On-chip communication topology synthesis for shared multi-bus based architecture
2005 · S. Pandey, M. Glesner, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 9
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic
2007 · Sujan Pandey, Manfred Glesner · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 8
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects
2007 · T. Murgan, P. B. Bacinschi, et al. · Lecture notes in computer science · 6
Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique
2006 · S. Pandey, M. Glesner · IEEE International Symposium on Circuits and Systems proceedings · 6
High level Hardware/Software Communication Estimation in Shared Memory Architecture
2005 · S. Pandey, H. Zimmer, et al. · IEEE International Symposium on Circuits and Systems proceedings · 6
Transient errors resiliency analysis technique for automotive safety critical applications
2014 · Sujan Pandey, Bart Vermeulen · Design, Automation, and Test in Europe · 5
Process variations aware robust on-chip bus architecture synthesis for MPSoCs
2008 · Sujan Pandey, Rolf Drechsler, et al. · IEEE International Symposium on Circuits and Systems proceedings · 4
Co-synthesis of custom on-chip bus and memory for MPSoC architectures
2007 · Sujan Pandey, Christian Genz, et al. · IFIP International Conference on Very Large Scale Integration (VLSI-SoC) · 4
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters
2006 · T. Murgan, O. Mitea, et al. · IFIP International Conference on Very Large Scale Integration (VLSI-SoC) · 4
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis
2006 · Sujan Pandey, Tudor Murgan, et al. · IFIP International Conference on Very Large Scale Integration (VLSI-SoC) · 3
An infrastructure for distributed computing and context aware computing
2003 · Sujan Pandey, Peter Zipf, et al. · TUbilio (Technical University of Darmstadt) · 3
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
2008 · Sujan Pandey, Rolf Drechsler · 2
Architecture level design space exploration and mapping of hardware
2006 · S. Pandey, M. Glesner, et al. · International Symposium on Signals, Circuits and Systems · 2
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture
2006 · Sujan Pandey, Nurten Utlu, et al. · IFIP International Conference on Very Large Scale Integration (VLSI-SoC) · 2
UbiComp device for a decentralized distributed computing environment
2004 · S. Pandey, P. Zipf, et al. · IEEE International Symposium on Signal Processing and Information Technology (ISSPIT) · 2
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
2008 · Sujan Pandey, Rolf Drechsler · Design, Automation, and Test in Europe · 1
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
2008 · Sujan Pandey, Rolf Drechsler · Asia and South Pacific Design Automation Conference (ASP-DAC) · 1
Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture
2006 · Sujan Pandey, Manfred Glesner · International Conference on Field Programmable Logic and Applications (FPL) · 1
System design and integration in pervasive appliances
2003 · Manfred Glesner, Tudor Murgan, et al. · 1
Soft-errors resilient logic optimization for low power
2012 · Sujan Pandey, Klaas Brink · IEEE International On-Line Testing Symposium (IOLTS)
Energy Conscious On-Chip Communication Bus Synthesis and Optimization for MPSoC Architectures
2008 · Pandey, Sujan · Technischen Universität Darmstadt
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Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip.
2005 · Thomas Hollstein, Sujan Pandey, et al. · Reconfigurable Communication-centric Systems-on-Chip
Works count: 25
Citation count: 94
H-index: 6
I10-index: 2
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