Work

Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress

Year: 2013

Type: article

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI: 10.1109/tvlsi.2013.2255628

Authors: Hyoyoung Shin, Youngkyu Park, Gihwa Lee, Jungsik Park, Sungho Kang

Institution: Yonsei University

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2114773166

FWCI: 1.115

Cites: 17

Cited by: 4

Related to: 10