An efficient automatic test generation system for path delay faults in combinational circuits
Year: 2002
Type: conference-paper
Authors: A.K. Majhi, J. Jacob, L.M. Patnaik, V.D. Agrawal
Institutions: Indian Institute of Science Bangalore, AT&T (United States)
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2139397375