Work

Scan-Chain Intra-Cell Aware Testing

Year: 2016

Type: article

Abstract: This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46 percent on average) and a shorter test time (i.e., 42.20 percent on average) than by straightforwardly using an ATPG which directly targets these defects.

Source: IEEE Transactions on Emerging Topics in Computing

DOI: 10.1109/tetc.2016.2624311

Authors: Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray

Institutions: Centre National de la Recherche Scientifique, Université de Montpellier, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Politecnico di Torino, STMicroelectronics (France)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2550020175

FWCI: 1.723

Cites: 11

Cited by: 10

Related to: 10