Work

Self-timed automatic test pattern generation for null convention logic

Year: 2016

Type: conference-paper

Source: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

DOI: 10.1109/mwscas.2016.7870032

Authors: Nastaran Nemati, Mark C. Reed, Sri Parameswaran, Karl Fant

Institution: UNSW Sydney

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2594420159

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Cites: 13

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Related to: 10