Work

A Dynamic Power Reduction in Synchronous 2RW 8T Dual-Port SRAM by Adjusting Wordline Pulse Timing with Same/Different Row Access Mode

Year: 2018

Type: article

Source: IEICE Technical Report; IEICE Tech. Rep.

Authors: Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii

Institution: Renesas Electronics (Japan)

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2799418142

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Related to: 20