Blocking Performance Improvements for 4H-SiC P-GTO Thyristors with Carrier Lifetime Enhancement Processes
Year: 2018
Type: article
Abstract: An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2 between amorphous SiO2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VF over the 1300°C oxidized devices, without any impact on blocking characteristics.
Source: Materials science forum
Authors: Sei Hyung Ryu, Daniel J. Lichtenwalner, Michael O'Loughlin, Edward van Brunt, Craig Capell, Charlotte Jonas, Yemane Lemma, Qing Chun Zhang, Jim Richmond, Albert Burk, Brett Hull, Matthew McCain, Shadi Sabri, Heather O'Brien, Aderinto Ogunniyi, Aivars J. Lelis, Jeff Casady, David Grider, Scott Allen, John W. Palmour
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W2809938152