Work

Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology

Year: 2023

Type: article

Abstract: This article describes a method to improve test quality by explicitly targeting realistic cell-internal open and short defects through dedicated technology cell-level test patterns. The authors report some of the earliest results of their cell-aware test methods on an advanced 3-nm technology library from IMEC.

Source: IEEE Design and Test

DOI: 10.1109/mdat.2023.3294872

Authors: Zhan Gao, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen

Institutions: IMEC, Cadence Design Systems (United States), Eindhoven University of Technology

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green

Funders: Cadence Design Systems, China Scholarship Council

OpenAlex ID: W4384080896

FWCI: 0.171

Cites: 12

Cited by: 1

Related to: 10