Work

CODESCA: Co-Design for Spectral Clustering Acceleration

Year: 2026

Type: conference-abstract

Abstract: : Spectral clustering is powerful but limited by O(N³) complexity. We present CODESCA, a co-design on Xilinx VCK190. By offloading sparse graph construction to the host and utilizing a quantization-aware block power iteration engine on FPGA, CODESCA achieves 22× speedup over CPU and 9× better throughput-per-watt than RTX 3080 GPU, enabling efficient edge data mining.

Source: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

DOI: 10.1145/3748173.3779550

Authors: Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk

Institutions: Tianjin University, Imperial College London

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: hybrid

OpenAlex ID: W7127933952

Cites:

Cited by:

Related to: 10