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V. Thamizharasan

Observed names: Thamizharasan .V, Thamizharasan V, Thamizharasan. V
ORCID: 0000-0001-7896-7164
Observed ORCID: 0000-0001-7896-7164
OpenAlex ID: A5004332291
Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation
2024 · V. Thamizharasan, V. Parthipan · Scientific Reports · 40
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FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier
2022 · V. Thamizharasan, N. Kasthuri · International Journal of Electronics · 40
High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation
2021 · V. Thamizharasan, N. Kasthuri · IETE Journal of Research · 39
Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation
2022 · V. Thamizharasan, N. Kasthuri · IETE Journal of Research · 19
FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder
2023 · V. Thamizharasan, N. Kasthuri · International Journal of Electronics · 16
An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier
2012 · Thamizharasan .V, Parthipan.V Parthipan.V · International Journal of Computer Applications · 12
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FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures
2025 · V. Thamizharasan, V. Parthipan · International Journal of Electronics · 3
Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder
2023 · V. Thamizharasan, Gokulapriya M., et al. · International Journal of Computer Applications · 3
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Design and FPGA Implementation of Efficient Multiplier Architecture using Reversible Logic
2025 · V. Thamizharasan, V. Parthipan · WSEAS Transactions on Signal Processing archive · 2
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Solar Powered Autonomous Robotic Car Using for Surveillance
2021 · V. Premchandran, M. Karthikkumar, et al. · Smart innovation, systems and technologies · 2
Comprehensive evaluation of performance of full adder cells for various operational condition and application
2025 · G. Prabhakaran, V. Thamizharasan, et al. · International Journal of Systems Assurance Engineering and Management · 1
A Generalized Scalar Pwm Approach for Three-phase Voltage-source Inverter Fed Ac Drive
2023 · V. Thamizharasan, M. Karthikkumar · International Journal of Electrical Engineering and Computer Science · 1
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Investigation on Power, Delay and Area optimization of XOR Gate
2021 · Thamizharasan. V, Ramya. M · WSEAS Transactions on Circuits and Systems archive · 1
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Design and FPGA implementation of an area and throughput-efficient LDPC encoder architecture using Python-based VeCoGen
2026 · Thamizharasan V, Suriyaprakash G, et al. · International Journal of Electronics Letters
Design and FPGA implementation of reversible vedic multipliy and accumulate unit for cryptography applications
2026 · V. Thamizharasan, A. Nikhil, et al. · Analog Integrated Circuits and Signal Processing
RETRACTED: Adaptive Beam forming algorithms for wireless Communication using LABVIEW
2021 · M. Ramya, V. Thamizharasan, et al. · IOP Conference Series Materials Science and Engineering
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Works count: 16
Citation count: 177
H-index: 6
I10-index: 6
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