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Arame Thiam

Observed name: A. Thiam
ORCID: 0000-0001-9814-0420
Observed ORCID: 0000-0001-9814-0420
OpenAlex ID: A5005195191
Nanoscale domain wall devices with magnetic tunnel junction read and write
2021 · E. Raymenants, O. Bultynck, et al. · Nature Electronics · 125
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Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab
2020 · I. Asselberghs, Q. Smets, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 65
WS2 transistors on 300 mm wafers with BEOL compatibility
2017 · T. Schram, Q. Smets, et al. · European Solid-State Device Research Conference · 43
Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB
2021 · Quentin Smets, Tom Schram, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 29
Fabrication and room temperature characterization of trilayer junctions for the development of superconducting qubits on 300 mm wafers
2021 · Danny Wan, Sebastian Couet, et al. · Japanese Journal of Applied Physics · 21
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First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP
2022 · G. Murdoch, M. O'Toole, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 19
InP HBT Thermal Management by Transferring to High Thermal Conductivity Silicon Substrate
2014 · Arame Thiam, Yannick Roelens, et al. · IEEE Electron Device Letters · 15
MP18–26 Ru Direct-Etch Integration Development with Leakage Improvement and Increased Aspect Ratio
2022 · Ankit Pokhrel, Giulio Marti, et al. · IEEE International Interconnect Technology Conference (IITC) · 13
Scaled transistors with 2D materials from the 300mm fab
2020 · I. Asselberghs, T. Schram, et al. · IEEE Silicon Nanoelectronics Workshop · 13
Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions
2018 · E. Raymenants, D. Wan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 13
Fabrication of magnetic tunnel junctions connected through a continuous free layer to enable spin logic devices
2018 · Danny Wan, Mauricio Manfrini, et al. · Japanese Journal of Applied Physics · 13
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Magnetic domain walls: from physics to devices
2021 · E. Raymenants, D. Wan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 11
All-Electrical Control of Scaled Spin Logic Devices Based on Domain Wall Motion
2021 · Eline Raymenants, Danny Wan, et al. · IEEE Transactions on Electron Devices · 11
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High yield and process uniformity for 300 mm integrated WS 2 FETs
2021 · T. Schram, Quentin Smets, et al. · Symposium on VLSI Technology · 10
Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells
2022 · V. Vega-Gonzalez, D. Radisic, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Low-loss, low-temperature PVD SiN waveguides
2021 · Negin Golshani, Thomas Witters, et al. · IEEE International Conference on Group IV Photonics (GFP) · 7
Today’s scorecard for tomorrow’s photoresist: progress and outlook towards High-NA EUV lithography
2021 · Jara G. SantaClara, Gijsbert Rispens, et al. · Advances in Patterning Materials and Processes · 7
All-electrical control of scaled spin logic devices based on domain wall motion
2020 · E. Raymenants, D. Wan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line
2017 · T. Schram, Q. Smets, et al. · Silicon Nanoelectronics Workshop (SNW) · 7
Advanced processes in metal-oxide resists for high-NA EUV lithography
2024 · Cong Que Dinh, Seiji Nagahara, et al. · Advances in Patterning Materials and Processes · 6
Recent advances in EUV patterning in preparation towards high-NA EUV
2023 · Seiji Nagahara, Arnaud Dauendorffer, et al. · Advances in Patterning Materials and Processes · 6
CMOS integration of high- k /metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits
2018 · Eugenio Dentoni Litta, Romain Ritzenthaler, et al. · Japanese Journal of Applied Physics · 5
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Advanced PnR logic patterning enabled by high-NA EUV lithography
2025 · Syamashree Roy, Arame Thiam, et al. · SPIE Optical and EUV Nanolithography · 4
Holistic litho-etch approach towards high NA EUV challenges
2023 · Soichiro Okada, Arnaud Dauendorffer, et al. · International Conference on Extreme Ultraviolet Lithography · 2
Pushing the boundaries of random logic metal patterning with low-n EUV single exposure
2024 · Syamashree Roy, Arame Thiam, et al. · SPIE Optical and EUV Nanolithography · 1
Works count: 33
Citation count: 462
H-index: 11
I10-index: 14
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