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Aneesh Raveendran

Observed name: Raveendran, Aneesh
OpenAlex ID: A5022564712
A RISC-V instruction set processor-micro-architecture design and analysis
2016 · Aneesh Raveendran, Vinayak Baramu Patil, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) · 55
Out of order floating point coprocessor for RISC V ISA
2015 · Vinayak Patil, Aneesh Raveendran, et al. · International Symposium on VLSI Design and Test (VDAT) · 33
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture
2020 · Aneesh Raveendran, Sandra Jean, et al. · International Conference on VLSI Design · 19
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor
2021 · Sandra Jean, Aneesh Raveendran, et al. · International Conference on VLSI Design · 11
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications
2023 · Pranose J Edavoor, Aneesh Raveendran, et al. · International Conference on VLSI Design · 8
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA
2020 · Vivian Desalphine, Somya Dashora, et al. · International Symposium on VLSI Design and Test (VDAT) · 7
Micro-Architecture Design and Analysis of AXI Enabled SHA-3 Hardware Accelerator for a RISC-V Based SoC
2025 · Aneesh Raveendran, Sheetal B V, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) · 6
BHARAT-TPM: Micro-Architecture Design of Scalable Hardware Random Number Generator for a RISC-V Trusted Platform Module
2026 · Soumya G Hosmani, Raja Sekar K, et al. · International Conference on VLSI Design · 5
A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications
2024 · Venkata Reddy Kolagatla, Aneesh Raveendran, et al. · International Symposium on VLSI Design and Test (VDAT) · 5
PositGen-A Verification Suite for Posit Arithmetic
2021 · Annarao Kulkarni, Shashikala Pattanshetty, et al. · International Conference on VLSI Design · 3
Design and Analysis of Posit Processing Engine with Embedded Activation Functions for Neural Network Applications
2023 · Pranose J. Edavoor, Aneesh Raveendran, et al. · Lecture notes in electrical engineering · 2
RISC-V out-of-order data conversion co-processor
2015 · Aneesh Raveendran, Vinayak Patil, et al. · International Symposium on VLSI Design and Test (VDAT) · 2
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled RNG Accelerator
2026 · Mahima Agarwal, Soumya G Hosmani, et al. · IEEE International Conference on Public Key Infrastructure and its Applications (PKIA)
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM4 Accelerator
2026 · Jeeshma T. N, Beautlin S, et al.
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM2-DSA Accelerator
2026 · Mahima Agarwal, Harish Kumar G, et al.
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled RSA-4096 Accelerator
2026 · Mahima Agarwal, Divya B, et al. · International Symposium on VLSI Design and Test (VDAT)
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled AES Accelerator
2026 · Mahima Agarwal, Bhavana B L, et al. · International Symposium on VLSI Design and Test (VDAT)
BHARAT-TPM: Micro-Architecture Design of AXI Enabled HMAC SHA-3 Hardware Accelerator for a RISC-V Trusted Platform Module
2026 · Adithyadev Mattada, Sheetal B V, et al. · International Symposium on VLSI Design and Test (VDAT)
BHARAT-TPM: Micro-Architecture Design of AXI Enabled SM3 Hardware Accelerator for a RISC-V Trusted Platform Module
2026 · Kiran P, Sheetal B V, et al. · International Symposium on VLSI Design and Test (VDAT)
BHARAT-TPM: Micro-architecture Design of AXI Enabled SHA-3 Hardware Accelerator for a RISC-V Trusted Platform Module
2026 · Aneesh Raveendran, B. V. Sheetal, et al. · Communications in computer and information science
BHARAT-TPM: Micro-Architecture Design of AXI Enabled AES Hardware Accelerator for RISC-V Trusted Platform Module
2026 · Bhavana Bl, Raja Sekar K, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing
2024 · Venkata Reddy Kolagatla, Aneesh Raveendran, et al. · International Symposium on VLSI Design and Test (VDAT)
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor
2019 · Aneesh Raveendran, Sandra Jean, et al. · Communications in computer and information science
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU
2019 · Aneesh Raveendran, Vinay Kumar, et al. · Communications in computer and information science
Works count: 25
Citation count: 156
H-index: 6
I10-index: 4
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