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Adam D Brand

Observed names: A. Brand, Adam Brand, Adam Brand (18669736)
ORCID: 0000-0003-1300-5292
Observed ORCID: 0000-0003-1300-5292
OpenAlex ID: A5042475721
Semiconductor Logic Technology Innovation to Achieve Sub-10 nm Manufacturing
2013 · Klaus Schuegraf, Mathew C. Abraham, et al. · IEEE Journal of the Electron Devices Society · 104
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Novel read disturb failure mechanism induced by FLASH cycling
1993 · A. Brand, K. Wu, et al. · IEEE International Reliability Physics Symposium proceedings · 91
An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V
2002 · S. Thompson, M. Alavi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62
HKMG process impact on N, P BTI: Role of thermal IL scaling, IL/HK integration and post HK nitridation
2013 · K. Joshi, S. Hung, et al. · IEEE International Reliability Physics Symposium proceedings · 60
Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET
2015 · C.-N. Ni, X. Li, et al. · Symposium on VLSI Technology · 39
Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
2012 · Aneesh Nainani, Shashank Gupta, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 37
15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
2014 · J. Mitard, L. Witters, et al. · Symposium on VLSI Technology · 35
Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond
2014 · L.-A. Ragnarsson, S. A. Chew, et al. · Symposium on VLSI Technology · 33
Fin Doping by Hot Implant for 14nm FinFET Technology and Beyond
2013 · Bingxi Sun Wood, Fareen Adeni Khaja, et al. · ECS Transactions · 30
Confidence bands in survival analysis
2022 · Michael C. Sachs, Adam Brand, et al. · British Journal of Cancer · 19
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A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications
2008 · R. Fastow, R. Banerjee, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 17
Threshold voltage tuning by metal gate work function modulation for 10 nm CMOS integration and beyond
2014 · Naomi Yoshida, Keping Han, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 16
Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology
2013 · Anabela Veloso, Soon Aik Chew, et al. · Japanese Journal of Applied Physics · 16
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RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs
2015 · L.-A. Ragnarsson, H. Dekkers, et al. · Symposium on VLSI Technology · 14
Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOx
2012 · K. Joshi, S. Hung, et al. · IEEE Electron Device Letters · 12
A Scalable Self-Aligned Contact NOR Flash Technology
2007 · M. Wei, R. Banerjee, et al. · Symposium on VLSI Technology · 11
Low power SRAM techniques for handheld products
2005 · Rabiul Islam, Adam Brand, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 9
Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation
2012 · C. Ni, X. Fu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 8
FinFET multi-Vt tuning with metal gate work function modulation by plasma doping
2014 · Keping Han, Jun Lee, et al. · International Workshop on Junction Technology · 7
Metal gate work function modulation by ion implantation for multiple threshold voltage FinFET devices
2013 · Keping Han, Peng-Fu Hsu, et al. · International Workshop on Junction Technology · 5
Enable abrupt junction and advanced salicide formation with dynamic surface annealing
2012 · Shiyu Sun, Shankar Muthukrishnan, et al. · Physica status solidi. C, Conferences and critical reviews/Physica status solidi. C, Current topics in solid state physics · 5
NMOS contact resistivity reduction with implants into silicides
2013 · K. V. Rao, Fareen Adeni Khaja, et al. · Physica status solidi. C, Conferences and critical reviews/Physica status solidi. C, Current topics in solid state physics · 4
NMOS contact resistance reduction with selenium implant into NiPt silicide
2012 · K. V. Rao, F. A. Khaja, et al. · AIP conference proceedings · 4
Contact barrier height and resistivity reduction using low work-function metal (Yb)-interfacial layer-semiconductor contacts on n-type Si and Ge
2015 · N. Remesh, S. Dev, et al. · Conference digest · 3
Selenium segregation optimization for 10 nm node contact resistivity
2014 · C.-N. Ni, K.V. Rao, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
Works count: 39
Citation count: 658
H-index: 14
I10-index: 16
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