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H. Brut

Observed names: Brut, H., Brut, Hugues, Hugues Brut
OpenAlex ID: A5058128381
Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling
2006 · Antoine Cros, Krunoslav Romanjek, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 137
New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs
2008 · Dominique Fleury, Antoine Cros, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 83
A New Combined Methodology for Write-Margin Extraction of Advanced SRAM
2007 · Nicolas Gierczynski, Bertrand Borot, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 78
New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs with Ultra-thin Gate Oxides
2002 · J. Pretet, T. Matsumoto, et al. · European Solid-State Device Research Conference · 77
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm 2 6T-SRAM bitcell
2007 · C. Fenouillet-Beranger, J. Todeschini, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 73
Highly performant double gate MOSFET realized with SON process
2004 · S. Harrison, P. Coronel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 56
A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform
2004 · F. Arnaud, F. Boeuf, et al. · Symposium on VLSI Technology · 31
Low cost 65nm CMOS platform for Low Power & General Purpose applications
2004 · F. Arnaud, B. Duriez, et al. · Symposium on VLSI Technology · 31
Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below
2008 · Dominique Fleury, Antoine Cros, et al. · IEEE Transactions on Semiconductor Manufacturing · 28
New extraction method for gate bias dependent series resistance in nanometric double gate transistors
2005 · A. Cros, S. Harrison, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 20
Nickel vs. cobalt silicide integration for sub-50nm CMOS
2004 · B. Froment, M. Muller, et al. · IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) · 19
Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform
2004 · B. Tavel, M. Bidaud, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors
2002 · H. Brut, A. Juge, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 15
Physical model of threshold voltage in siliconMOS transistors including reverse short channel effect
1995 · H. Brut, A. Juge, et al. · Electronics Letters · 15
Contribution to the characterization of the hump effect in MOSFET submicronic technologies
2003 · H. Brut, R.M.D.A. Velghe · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 13
A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs
2009 · Dominique Fleury, Antoine Cros, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 10
Gate stack optimization for 65 nm CMOS low power and high performance platform
2004 · B. Duriez, B. Tavel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 μm CMOS technology
2002 · R. Difrenza, P. Llinares, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 7
Automatic extraction methodology for accurate measurement of effective channel length on 65nm MOSFET technology and below
2007 · Dominique Fleury, Antoine Cros, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 5
70 GHZ FMAX fully-depleted SOI MOSFET’S for low-power wireless applications
2000 · Raynaud, C., Faynot, O., et al. · AMS Acta (University of Bologna) · 5
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Test chip characterization of X architecture diagonal lines for SoC design
2004 · N.D. Arora, L. Song, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 4
Accuracy improvement of the "Single Pattern Driver" method for the characterization of interconnect capacitance in the context of nanometer technology development
2004 · H. Brut, S. Martin, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 4
New Method for the Extraction of the Gate Voltage Dependence of the Series Resistance in CMOS Transistors
1996 · H. Brut, G. Ghibaudo, et al. · European Solid-State Device Research Conference · 4
Measurement of Capacitances in Multigate Transistors by Coulomb Blockade Spectroscopy
2008 · M. Hofheinz, X. Jehl, et al. · IEEE Transactions on Nanotechnology · 2
Experimental mobility study of DG-GAA MOSFETs down to 40nm gate length
2005 · Cros, A., Harrison, S., et al. · HAL · 1
Works count: 35
Citation count: 747
H-index: 14
I10-index: 16
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