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Kashi Vishwanath Machani

Observed names: K. V. Machani, K.V. Machani, Kashi Machani
ORCID: 0009-0002-1884-6795
Observed ORCID: 0009-0002-1884-6795
OpenAlex ID: A5058440554
Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application
2012 · F. Kuechenmeister, D. Breuer, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 23
CPI challenges to BEOL at 28nm node and beyond
2012 · Vivian Ryan, Dirk Breuer, et al. · IEEE International Reliability Physics Symposium proceedings · 19
Chip Package Interaction (CPI) risk assessment of 22FDX® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling
2020 · Kashi Vishwanath Machani, Frank Kuechenmeister, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 11
FEA study of damage and cracking risks in BEoL structures under copper wirebonding impact
2015 · J. Auersperg, D. Breuer, et al. · International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) · 11
Experimental analyses of the mechanical reliability of advanced BEOL/fBEOL stacks regarding CPI loading
2013 · H. Geisler, E. Schuchardt, et al. · IEEE International Reliability Physics Symposium proceedings · 11
A Generic Strategy to Assess and Mitigate Chip Package Interaction Risk Factors for Semiconductor Devices with Ultra-low k Dielectric Materials in Back End of Line
2017 · Frank Kuechenmeister, Dirk Breuer, et al. · IMAPSource Proceedings · 9
Mechanical reliability assessment of 28nm Back End of Line (BEoL) stack using finite element analysis and validation
2015 · Kashi Vishwanath Machani, Holm Geisler, et al. · IEEE International Reliability Physics Symposium proceedings · 7
Chip Package Interaction (CPI) Stress Modeling
2020 · Kashi Vishwanath Machani, Frank Kuechenmeister, et al. · International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) · 6
Temperature-dependent Creep Characterization of Lead-free Solder Alloys Using Nanoindentation for Finite Element Modeling
2023 · Viktor Dudash, Kashi Vishwanath Machani, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 5
Finite Element Model for Prediction of Back-End-of-Line Process Induced Wafer Bow for Patterned Wafer
2023 · Prashant Kumar Singh, Kashi Vishwanath Machani, et al. · International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) · 5
Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling
2023 · Viktor Dudash, Kashi Vishwanath Machani, et al. · IEEE International Reliability Physics Symposium proceedings · 5
Study on Effect of Microstructure Evolution on Wafer Warpage for High-Temperature Annealed and Self-Annealed Copper Thin Films
2025 · Prashant Kumar Singh, Maik Mueller, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 4
Characterization and Modeling of Solder Interconnects for Wafer Level Packaging Applications Subjected to Low Cycle Fatigue Stress
2025 · V. Dudash, K. V. Machani, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2
Creep characterization of lead-free solder alloys over an extended temperature range used for fatigue modeling
2024 · Viktor Dudash, Kashi Vishwanath Machani, et al. · International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) · 2
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
2023 · Prashant Kumar Singh, Patrick Rohlfs, et al. · European Microelectronics and Packaging Conference · 2
Design of Reliability Test Assemblies for WLCSP Solder Interconnects using Finite Element Modeling
2022 · Viktor Dudash, Karsten Meier, et al. · International Spring Seminar on Electronics Technology · 2
Temperature-Dependent Material Characterization of Back-End-of-Line Copper with Nanoindentation for FEM-Based Wafer Warpage Prediction
2025 · Prashant Kumar Singh, Holm Geisler, et al. · International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) · 1
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
2024 · Prashant Kumar Singh, Patrick Rohlfs, et al. · IMAPSource Proceedings · 1
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Influence of Annealing on Microstructure of Electroplated Copper Trenches in Back-End-Of-Line
2023 · Prashant Kumar Singh, Maik Müller, et al. · IEEE International Interconnect Technology Conference and IEEE Materials for Advanced Metallization Conference (IITC/MAM) · 1
Chip-Package Interaction: A Case Study Applied To A Mature Technology Node
2023 · Eng Chye Chua, Frank Kuechenmeister, et al. · IEEE Electronics Packaging Technology Conference (EPTC)
Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEoL) Silicon, Cu Pillar Design and Applied Process Improvements
2018 · Frank Kuechenmeister, Dirk Breuer, et al. · IMAPSource Proceedings
FEA to Tackle Damage and Cracking Risks in BEoL Structures under Copper Wire Bonding Impact
2016 · J. Auersperg, D. Breuer, et al. · Qucosa (Saxon State and University Library Dresden)
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Understanding the Fundamentals for Package Induced Failure in BEOL Interconnect at 20nm Node
2013 · Vivian Ryan, Shan Gao, et al. · MRS Proceedings
Microprobing the mechanical effects of varying dielectric porosity in advanced interconnect structures
2012 · Alexander Hsing, Holm Geisler, et al. · IEEE International Interconnect Technology Conference (IITC)
Works count: 24
Citation count: 127
H-index: 7
I10-index: 5
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