Get started
Author

Yasushi Tateshita

5.7 A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance
2020 · Yorito Sakano, Takahiro Toyoshima, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 54
A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation
2018 · S. Iida, Y. Sakano, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 44
Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process
2007 · J. Wang, Y. Tateshita, et al. · Symposium on VLSI Technology · 28
Intercalation of lithium in r.f.-sputtered niobium oxide film as electrode material for lithium-ion batteries
1995 · Naoaki Kumagai, Yasushi Tateshita, et al. · Journal of Power Sources · 26
High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates
2006 · Y. Tateshita, J. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 25
High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates
2009 · Satoru Mayuzumi, Shinya Yamakawa, et al. · IEEE Transactions on Electron Devices · 23
Back-Illuminated $2.74 \ \mu \mathrm{m}$ -Pixel-Pitch Global Shutter CMOS Image Sensor with Charge-Domain Memory Achieving 10k e-Saturation Signal
2018 · Y. Kumagai, R. Yoshita, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates
2007 · S. Mayuzumi, J. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
Three-dimensional structures for high saturation signals and crosstalk suppression in 1.20 μm pixel back-illuminated CMOS image sensor
2013 · T. Shinohara, K. Watanabe, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Mobility and Velocity Enhancement Effects of High Uniaxial Stress on Si (100) and (110) Substrates for Short-Channel pFETs
2010 · Satoru Mayuzumi, Shinya Yamakawa, et al. · IEEE Transactions on Electron Devices · 13
Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe
2009 · Satoru Mayuzumi, Shinya Yamakawa, et al. · IEEE Transactions on Electron Devices · 13
Channel-stress study on gate-size effects for damascene-Gate pMOSFETs with top-cut compressive stress liner and eSiGe
2008 · S. Mayuzumi, S. Yamakawa, et al. · Symposium on VLSI Technology · 9
High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology
2006 · S. Yamaguchi, K. Tai, et al. · Symposium on VLSI Technology · 9
A $2.9\mu \mathrm{m}$ Pixel CMOS Image Sensor for Security Cameras with high FWC and 97 dB Single-Exposure Dynamic Range
2021 · T. Uchida, K. Yamashita, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Study of stress effect on replacement gate technology with compressive stress liner and eSiGe for pFETs
2008 · S. Yamakawa, S. Mayuzumi, et al. · International Conference on Simulation of Semiconductor Processes and Devices · 6
Threshold Voltage Modulation Technique using Fluorine Treatment through Atomic Layer Deposition TiN Suitable for Complementary Metal–Oxide–Semiconductor Devices
2008 · Kaori Tai, Shinpei Yamaguchi, et al. · Japanese Journal of Applied Physics · 6
Comparative study between Si (110) and (100) substrates on mobility and velocity enhancements for short-channel highly-strained PFETs
2006 · Satoru Mayuzumi, Shuji Yamakawa, et al. · Symposium on VLSI Technology · 6
Effects of Channel Width on Stress Enhancement for Damascene-Gate nFETs With Top-Cut Tensile-Stress Liner
2009 · S. Mayuzumi, S. Yamakawa, et al. · IEEE Electron Device Letters · 5
Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application
2006 · T. Ando, T. Hirano, et al. · Symposium on VLSI Technology · 5
Analysis of Novel Stress Enhancement Effect Based on Damascene Gate Process with eSiGe S/D for pFETs
2007 · S. Yamakawa, J. Wang, et al. · Springer eBooks · 4
High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process
2006 · K. Tai, T. Hirano, et al. · European Solid-State Device Research Conference · 4
Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone–Water-Last Treatment
2008 · Itaru Oshiyama, Kaori Tai, et al. · Japanese Journal of Applied Physics · 3
Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner
2009 · S. Mayuzumi, S. Yamakawa, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 2
Stress enhancement concept on replacement gate technology with top-cut stress liner for nFETs
2008 · S. Yamakawa, S. Mayuzumi, et al. · European Solid-State Device Research Conference · 2
High performance nMOSFET with HfSi/subx//HfO/sub 2/ gate stack by low temperature process
2006 · T. Hirano, T. Ando, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Works count: 38
Citation count: 362
H-index: 11
I10-index: 11
Year
Topic
Type