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S. Eichenberger
Observed name:
Stefan Eichenberger
Institution:
NXP (Netherlands)
Observed institutions:
NXP (Netherlands),
Philips (Netherlands),
NXP (Germany)
OpenAlex ID:
A5074964895
On hazard-free patterns for fine-delay fault testing
2005
·
B. Kruseman
, A.K. Majhi
, et al.
·
IEEE International Test Conference (ITC)
·
108
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs
2009
·
F. Hapke
, R. Krenz-Baath
, et al.
·
IEEE International Test Conference (ITC)
·
95
Power Supply Noise in Delay Testing
2006
·
Jing Wang
, D. M. H. Walker
, et al.
·
IEEE International Test Conference (ITC)
·
80
Systematic defects in deep sub-micron technologies
2005
·
B. Kruseman
, A. Majhi
, et al.
·
IEEE International Test Conference (ITC)
·
69
Delay defect screening using process monitor structures
2004
·
S. Mitra
, E. Volkerink
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
68
An effective diagnosis method to support yield improvement
2003
·
C. Hora
, R. Segers
, et al.
·
IEEE International Test Conference (ITC)
·
65
Defect-oriented cell-internal testing
2010
·
F. Hapke
, W. Redemund
, et al.
·
IEEE International Test Conference (ITC)
·
54
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality
2008
·
S. Eichenberger
, J. Geuzebroek
, et al.
·
IEEE International Test Conference (ITC)
·
43
Modeling Power Supply Noise in Delay Testing
2007
·
Jing Wang
, D.M. Walker
, et al.
·
IEEE Design & Test of Computers
·
28
Gate-Exhaustive and Cell-Aware pattern sets for industrial designs
2011
·
Friedrich Hapke
, Juergen Schloeffel
, et al.
·
International Symposium on VLSI Design, Automation and Test
·
21
Full Open Defects in Nanometric CMOS
2008
·
Daniel Arumi
, Rosa Rodriguez-Montanes
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
15
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
2005
·
A.K. Majhi
, M. Azimane
, et al.
·
Design, Automation, and Test in Europe
·
14
PDF
Impact of gate tunnelling leakage on CMOS circuits with full open defects
2007
·
R. Rodríguez-Montañés
, D. Arumí
, et al.
·
Electronics Letters
·
12
Localization and Electrical Characterization of Interconnect Open Defects
2010
·
Rosa Rodriguez-Montanes
, Daniel Arumi
, et al.
·
IEEE Transactions on Semiconductor Manufacturing
·
11
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
2003
·
Camelia Hora
, Rene Segers
, et al.
·
Journal of Electronic Testing
·
10
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages
2007
·
D. Arumi
, R. Rodriguez-Montanes
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
9
I DDQ -based diagnosis at very low voltage (VLV) for bridging defects
2007
·
D. Arumi
, R. Rodríguez-Montañés
, et al.
·
Electronics Letters
·
9
Gate Leakage Impact on Full Open Defects in Interconnect Lines
2010
·
Daniel Arumi
, Rosa Rodriguez-Montanes
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
8
Time-dependent Behaviour of Full Open Defects in Interconnect Lines
2008
·
R. Rodriguez-Montanes
, D. Arumi
, et al.
·
IEEE International Test Conference (ITC)
·
6
Improving diagnostic resolution of delay faults using path delay fault model
2003
·
A.K. Majhi
, G. Gronthoud
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
6
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out
2011
·
Daniel Arumi
, Rosa Rodriguez-Montanes
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
5
Impact of Temperature on Test Quality
2010
·
Lavanya Jagan
, Camelia Hora
, et al.
·
International Conference on VLSI Design
·
5
Towards High Accuracy Fault Diagnosis of Digital Circuits
2004
·
Camelia Hora
, Stefan Eichenberger
·
Proceedings - International Symposium for Testing and Failure Analysis
·
4
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents
2013
·
Daniel Arumi
, Rosa Rodriguez-Montanes
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
2
Memory testing improvements through different stress conditions
2005
·
A. Majhi
, M. Azimane
, et al.
·
European Solid-State Circuits Conference (ESSCIRC)
·
1
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Works count:
28
Citation count:
748
H-index:
12
I10-index:
15
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