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Yeh-Jen Huang

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
2010 · C.C. Wu, D.W. Lin, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 112
Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure
2009 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 27
Investigation on the Validity of Holding Voltage in High-Voltage Devices Measured by Transmission-Line-Pulsing (TLP)
2008 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE Electron Device Letters · 25
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection
2022 · Jian-Hsing Lee, Yeh-Jen Huang, et al. · IEEE International Reliability Physics Symposium proceedings · 19
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration
2008 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 15
Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
2009 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE International Symposium on Circuits and Systems proceedings · 12
The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit
2024 · Jian-Hsing Lee, Yeh-Jen Huang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 7
Unipolar Arc Ignited Partial Discharge for 650-V AlGaN/GaN HEMTs during the DC Breakdown Voltage Measurement
2022 · Jian-Hsing Lee, Chih-Cherng Liao, et al. · Energies · 7
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A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event
2023 · Jian-Hsing Lee, Ching-Ho Li, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 5
Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity
2015 · Kai-Neng Tang, Seian-Feng Liao, et al. · Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC) · 5
An Area-Saving and Low-Leakage ESD Protection Circuit for 650V E-Mode GaN-HEMT
2025 · Jian-Hsing Lee, Yeh-Jen Huang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 2
ESD protection design with latchup-free immunity in 120V SOI process
2015 · Yi-Jie Huang, Ming-Dou Ker, et al. · IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference · 2
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection
2015 · Seian-Feng Liao, Kai-Neng Tang, et al. · European Conference on Circuit Theory and Design · 1
A Simple Layout Scheme to Enhance the ESD Robustness of UHV-LDMOS Devices in HVICs
2026 · Yeh-Jen Huang, Li-Yang Hong, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)
A Comprehensive Study of the Current Paths of HV IO Transistor During the Latch-Up Test
2025 · Jian-Hsing Lee, Chien-Wei Wang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
A Simple Scheme to Enhance the ESD Robustness of JFET in Startup Circuit
2025 · Yeh-Jen Huang, Li-Yang Hong, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)
Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power
2024 · Yeh-Jen Huang, Li-Yang Hong, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)
Works count: 17
Citation count: 239
H-index: 7
I10-index: 6
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