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Walter Anheier

Observed names: Anheier, Walter, Dr. W. Anheier, W. Anheier
OpenAlex ID: A5083499070
An image analysis system for automatic data acquisition from colored scanned maps
1994 · N. Ebi, B. Lauterbach, et al. · Machine Vision and Applications · 36
Efficient VLSI implementation of modern symmetric block ciphers
2003 · A. Schubert, W. Anheier · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 19
On Random Pattern Testability of Cryptographic VLSI Cores
2000 · A. Schubert, W. Anheier · Journal of Electronic Testing · 17
Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series
2003 · A.K. Palit, G. Doeding, et al. · IEEE International Conference on Fuzzy Systems (FUZZ-IEEE) · 16
Crosstalk fault modeling in defective pair of interconnects
2007 · Ajoy K. Palit, Kishore K. Duganapalli, et al. · Integration · 14
ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips
2005 · A.K. Palit, V. Meyer, et al. · International Conference on VLSI Design · 12
Decoupled victim model for the analysis of crosstalk noise between on-chip coupled interconnects
2009 · Ajoy K. Palit, Shehzad Hasan, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 11
Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model
2004 · A.K. Palit, V. Meyer, et al. · Proceedings · 10
Rigorous numerical analysis of a planar thyristor
1975 · W. Anheier, W.L. Engl, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
Reusable cryptographic VLSI core based on the SAFER K-128 algorithm with 251.8 Mbit/s throughput
2002 · A. Schubert, V. Meyer, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 8
Numerical analysis of gate triggered SCR turn-on transients
1977 · W. Anheier, W.L. Engl, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays
2009 · Shehzad Hasan, Ajoy K. Palit, et al. · IEEE Workshop on Signal Propagation on Interconnects (SPI) · 7
Segmentation of Scanned Maps in Uniform Color Spaces.
1994 · B. Lauterbach, W. Anheier · 7
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults
2010 · Shehzad Hasan, Ajoy K. Palit, et al. · International Conference on VLSI Design · 6
Reduction of Crosstalk Pessimism Using Tendency Graph Approach
2006 · Murthy Palla, Klaus Koch, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 6
Automated implementation of RNS-to-binary converters
2002 · H. Henkelmann, A. Drolshagen, et al. · IEEE International Symposium on Circuits and Systems proceedings · 6
A new approach for the speed up of fractal image coding
2002 · B. Rejeb, W. Anheier · IEEE International Conference on Digital Signal Processing (DSP) · 6
Processor elements for the standard cell implementation of residue number systems
2002 · A. Droishagen, H. Henkelmann, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 6
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk
2008 · Murthy Palla, Jens Bargfrede, et al. · International Symposium on Quality Electronic Design (ISQED) · 5
Real-time implementation of fractal image encoder
2005 · B. Rejeb, W. Anheier · IEEE Mediterranean Electrotechnical Conference (MELECON) · 5
On random pattern testability of cryptographic VLSI cores
2003 · A. Schubert, W. Anheier · IEEE European Test Symposium (ETS) · 5
Distributed RLGC transient model of coupled interconnects in DSM chips for crosstalk noise simulation
2008 · A.K. Palit, S. Hasan, et al. · Electronic System-Integration Technology Conference (ESTC) · 4
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips
2005 · A.K. Palit, Lei Wu, et al. · Proceedings - Asian Test Symposium/Proceedings · 4
Implementation of sign detection in RNS using mixed radix representation
2003 · H. Henkelmann, W. Anheier · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 4
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in both Defective and Defect-free Interconnects
2007 · Ajoy K. Palit, Kishore K. Duganapalli, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 3
Works count: 83
Citation count: 265
H-index: 9
I10-index: 8
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