Get started
Author

Raja Sekar Kumaresan

Observed names: K Raja Sekar, K. Raja Sekar, Raja Sekar K
ORCID: 0000-0002-7541-4203
Observed ORCID: 0000-0002-7541-4203
OpenAlex ID: A5107897811
Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique
2019 · Marshal Raj, Raja Sekar Kumaresan, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 9
Area-Efficient D-Flip Flop and XOR in QCA
2020 · Raja Sekar Kumaresan, Marshal Raj, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 7
Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology
2022 · Raja Sekar Kumaresan, Marshal Raj, et al. · Journal of Electrical Engineering · 4
PDF
Area Efficient Reliable QCA Adder and Subtractor
2023 · Anantharaj Thalaimalai Vanaraj, Raja Sekar K, et al. · International Conference on Integrated Circuits and Communication Systems (ICICACS) · 3
Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs
2022 · Anantharaj Thalaimalai Vanaraj, K Raja Sekar, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 3
Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs
2022 · Anantharaj Thalaimalai Vanaraj, Raja Sekar K, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 3
Framework for QCA Layout Generation and Rules for Rotated Cell Design
2022 · Raja Sekar Kumaresan, Marshal Raj, et al. · Journal of Circuits Systems and Computers · 2
High Speed Controllable Inverter for Adder-Subtractor in QCA
2019 · Marshal Raj, Raja Sekar Kumaresan, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 2
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata
2022 · Marshal Raj, K. Raja Sekar, et al. · IEEE Design and Test · 1
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled RNG Accelerator
2026 · Mahima Agarwal, Soumya G Hosmani, et al. · IEEE International Conference on Public Key Infrastructure and its Applications (PKIA)
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM4 Accelerator
2026 · Jeeshma T. N, Beautlin S, et al.
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM2-DSA Accelerator
2026 · Mahima Agarwal, Harish Kumar G, et al.
Intelligent Sensing in Orbit: A Multi-Stage Framework for Energy-Aware Adaptive Sampling in CubeSat Networks
2026 · A. A. Kadar, Sourav Sarker, et al. · Unmanned Systems
BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled AES Accelerator
2026 · Mahima Agarwal, Bhavana B L, et al. · International Symposium on VLSI Design and Test (VDAT)
BHARAT-TPM: Micro-Architecture Design of AXI Enabled SM3 Hardware Accelerator for a RISC-V Trusted Platform Module
2026 · Kiran P, Sheetal B V, et al. · International Symposium on VLSI Design and Test (VDAT)
A unified key generation accelerator with polynomials sampling and inversion units for post quantum NTRU-HRSS scheme
2026 · Soumya G Hosmani, A David Selvakumar, et al. · Sadhana
Designing Fault-Tolerant Digital Circuits in Quantum-Dot Cellular Automata
2024 · R. Marshal, K. Raja Sekar, et al. · Springer eBooks
Physically Realizable Reversible Logic Gates in Beyond CMOS QCA Technology
2023 · Lakshminarayanan Gopalakrishnan, R Marshal, et al. · CRC Press eBooks
Works count: 18
Citation count: 34
H-index: 3
I10-index:
Year
Topic
Type