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Olivier Faynot

Observed names: Faynot P. Rivallin Y. Cayrefourcq S. Cristoloveanu S. Deleonibus, O., Faynot, O, Faynot, O., Faynot, Olivier, Franc¸ois Andrieu, Olivier Weber, Marie-Anne Jaud, Thomas Ernst, and Olivier Faynot, O Faynot, O. FAYNOT, O. Faynot, O. Faynot A, O., Faynot, OLIVIER FAYNOT, Oliver Faynot, Olivier Faynotœ
Observed institutions: Institut polytechnique de Grenoble, Soitec (France), Universitat Autònoma de Barcelona, Centre National de la Recherche Scientifique, IBM (United States), Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Micro and Nanotechnology Innovation Centre, CEA Grenoble, STMicroelectronics (France), Direction de la Recherche Technologique, Institut Nanosciences et Cryogénie, Dolphin Design (France), Institut de Microélectronique, Electromagnétisme et Photonique, Institut Néel, Laboratoire d'Électronique des Technologies de l'Information, Centre de Radiofréquences, Optique et Micro-nanoélectronique des Alpes, IBM Research - Albany, Université Grenoble Alpes, Technical University of Denmark
OpenAlex ID: A5110023410
Low-Power Electronics Design
2010 · Massoud Pedram, Vojin G. Oklobdzija, et al. · CRC Press eBooks · 276
Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm
2012 · S. Barraud, M. Berthome, et al. · IEEE Electron Device Letters · 262
Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
2011 · Jean-Philippe Noel, Olivier Thomas, et al. · IEEE Transactions on Electron Devices · 200
High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
2008 · O. Weber, O. Faynot, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 167
Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs
2006 · V. Ferlet-Cavrois, P. Paillet, et al. · IEEE Transactions on Nuclear Science · 156
Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm
2012 · S. Barraud, R. Coquand, et al. · IEEE Electron Device Letters · 152
Advances, challenges and opportunities in 3D CMOS sequential integration
2011 · P. Batude, M. Vinet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 152
3DVLSI with CoolCube process: An alternative path to scaling
2015 · P. Batude, C. Fenouillet-Beranger, et al. · Symposium on VLSI Technology · 145
FDSOI devices with thin BOX and ground plane integration for 32nm node and below
2009 · C. Fenouillet-Beranger, S. Denorme, et al. · Solid-State Electronics · 138
Multiple gate devices: advantages and challenges
2005 · T. Poiroux, M. Vinet, et al. · Microelectronic Engineering · 131
GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current
2010 · L. Hutin, C. Le Royer, et al. · IEEE Electron Device Letters · 121
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
2016 · S. Barraud, V. Lapras, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 118
Advances in 3D CMOS sequential integration
2009 · P. Batude, M. Vinet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 118
15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET
2008 · C. Dupre, A. Hubert, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 111
BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control
2012 · Sourabh Khandelwal, Yogesh Singh Chauhan, et al. · IEEE Transactions on Electron Devices · 104
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
2010 · O. Faynot, F. Andrieu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 104
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
2010 · F. Andrieu, O. Weber, et al. · Symposium on VLSI Technology · 103
Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices
2005 · V. Ferlet-Cavrois, P. Paillet, et al. · IEEE Transactions on Nuclear Science · 97
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
2013 · Q. Liu, M. Vinet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 95
Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations
2002 · V. Ferlet-Cavrois, G. Gasiot, et al. · IEEE Transactions on Nuclear Science · 95
14nm FDSOI technology for high speed and energy efficient applications
2014 · O. Weber, E. Josse, et al. · Symposium on VLSI Technology · 94
A simple parameter extraction method for ultra-thin oxide MOSFETs
1995 · P.K McLarty, S Cristoloveanu, et al. · Solid-State Electronics · 92
First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
2016 · L. Brunet, P. Batude, et al. · Symposium on VLSI Technology · 88
Total ionizing dose effects on deca-nanometer fully depleted SOI devices
2005 · P. Paillet, M. Gaillardin, et al. · IEEE Transactions on Nuclear Science · 87
Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node
2013 · Marc Gaillardin, Martial Martinez, et al. · IEEE Transactions on Nuclear Science · 81
Works count: 488
Citation count: 8,780
H-index: 49
I10-index: 189
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