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Nitin Borkar

Observed names: Borkar Nitin, N Borkar, N. Borkar, N.Y. Borkar
Observed institution: Intel (United States)
OpenAlex ID: A5112900267
A 5-GHz Mesh Interconnect for a Teraflops Processor
2007 · Y. Hoskote, S. Vangal, et al. · IEEE Micro · 688
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
2007 · Sriram Vangal, Jason Howard, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 635
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
2008 · S.R. Vangal, J. Howard, et al. · IEEE Journal of Solid-State Circuits · 631
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
2010 · Jason Howard, Saurabh Dighe, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 607
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
2010 · J Howard, S Dighe, et al. · IEEE Journal of Solid-State Circuits · 401
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS
2012 · Shailendra Jain, Surhud Khare, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 272
The 48-core SCC Processor: the Programmer's View
2010 · Timothy G. Mattson, Michael Riepen, et al. · International Conference for High Performance Computing, Networking, Storage and Analysis (SC) · 239
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging
2007 · James Tschanz, Nam Sung Kim, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 226
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor
2010 · S Dighe, S R Vangal, et al. · IEEE Journal of Solid-State Circuits · 136
A 2 Tb/s 6 $\,\times\,$ 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS
2011 · P Salihundam, S Jain, et al. · IEEE Journal of Solid-State Circuits · 105
Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique
2004 · S. Narendra, J. Tschanz, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 85
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization
2006 · S.R. Vangal, Y.V. Hoskote, et al. · IEEE Journal of Solid-State Circuits · 69
1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS
2003 · S. Narendra, M. Haycock, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 65
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor
2010 · S. Dighe, S. Vangal, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 59
A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor
2007 · Muhammad Khellah, Dinesh Somasekhar, et al. · IEEE Journal of Solid-State Circuits · 58
A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS
2003 · Y. Hoskote, B.A. Bloechel, et al. · IEEE Journal of Solid-State Circuits · 45
Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing
2003 · J. Tschanz, Yibin Ye, et al. · Symposium on VLSI Circuits · 43
5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS
2002 · S. Vangal, M.A. Anders, et al. · IEEE Journal of Solid-State Circuits · 35
A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
2007 · Sriram Vangal, Arvind Singh, et al. · Symposium on VLSI Circuits · 31
A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS
2006 · M. Khellah, Nam Sung Kim, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 31
A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS
2010 · Praveen Salihundam, Shailendra Jain, et al. · Symposium on VLSI Circuits · 22
Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits
2009 · Muhammad Khellah, Nam Sung Kim, et al. · IEEE Journal of Solid-State Circuits · 22
A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS
2003 · S. Vangal, Y. Hoskote, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes
2002 · R. Nair, N.Y. Borkar, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 18
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm
2010 · Shailendra Jain, Vasantha Erraguntla, et al. · International Conference on VLSI Design · 17
Works count: 40
Citation count: 4,658
H-index: 22
I10-index: 31
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