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P. Poechmueller

Observed names: P. POECHMUELLER, P. Pochmuller, Peter Poechmueller, Peter Pöchmüller, Pöchmüller, Peter
OpenAlex ID: A5020161854
Fault-tolerant designs for 256 Mb DRAM
1996 · T. Kirihata, Y. Watanabe, et al. · IEEE Journal of Solid-State Circuits · 35
A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture
1999 · T. Kirihata, G. Mueller, et al. · IEEE Journal of Solid-State Circuits · 18
A 286 mm/sup 2/ 256 Mb DRAM with ×32 both-ends DQ
1996 · Y. Watanabe, Hing Wong, et al. · IEEE Journal of Solid-State Circuits · 10
High-level synthesis in a rapid-prototype environment for mechatronic systems
2003 · N. Wehn, H.-J. Herpel, et al. · European Design Automation Conference (EURO-DAC) · 8
HADES-high-level architecture development and exploration system
2002 · P. Poechmueller, M. Held, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 8
High-level synthesis transformations for programmable architectures
2002 · P. Pochmuller, M. Glesner, et al. · European Design Automation Conference (EURO-DAC) · 4
On the retention time distribution of dual-channel vertical DRAM technologies
2004 · J. Beintner, Y. Li, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell
2003 · S. Wuensche, M. Jacunski, et al. · Symposium on VLSI Circuits · 2
Memory management for high level synthesis applications
2003 · P. Pochmuller, M. Glesner · Annual IEEE International ASIC Conference and Exhibit · 2
Novel ASIC architecture and synthesis methodologies for future multiplexed datapath designs
2002 · F. Catthoor, N. Wehn, et al. · Annual European Computer Conference (CompEuro) · 2
Semiconductor Application Fail Root Causes And Secure Test Remedy
2024 · Heguo Yin, Peter Poechmueller · IEEE European Test Symposium (ETS) · 1
Design methodology for systematic derivation of fault-tolerant array processors
2003 · D.J. Soudris, P. Poechmueller, et al. · IEEE Computer Society European Conference (CompEuro) · 1
A CAD tool for designing large, fault-tolerant VLSI arrays
2002 · P. Poechmueller, G.K. Sharma, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 1
A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ
2002 · Y. Watanabe, H. Wong, et al. · Symposium on VLSI Circuits · 1
Design methodology for systematic derivation of fault-tolerant processor array architectures
1998 · D. SOUDRIS, P. POECHMUELLER, et al. · International Journal of Electronics · 1
High level synthesis in an FPGA-based computer aided prototyping environment
1993 · P. Poechmueller, H. -J. Herpel, et al. · Lecture notes in computer science · 1
Multilevel simulation tool for designing fault-tolerant VLSI array processors
1991 · P. Poechmueller, G.K. Sharma, et al. · International Conference on VLSI Design · 1
Silent Data Corruption (SDC) and No Trouble Found (NTF): Ways of Improving Test Towards 0 ppm
2026 · Heguo Yin, Kang Wan, et al. · Electronics
Flexibles KI-Deployment und KI-Plattformen für eingebettete, automotive Anwendungen (Akronym: MANNHEIM-FlexKI
2025 · Pöchmüller, Peter · RENATE
A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture
2003 · T. Kirihata, G. Mueller, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
An approach for multilevel logic cell optimization in module generators
2002 · P. Poechmueller, M. Glesner · ACM Great Lakes Symposium on VLSI (GLSVLSI)
EUROSYSTEMS-an industry/university advanced system design education project
2002 · P. Pochmuller, M. Glesner, et al. · Biennial University/Government/Industry Microelectronics Symposium
A 286 mm 2 256 Mb DRAM with ×32 Both-Ends DQ.
1995 · Yohji Watanabe, Hing Wong, et al.
Automatic Synthesis for Mechatronic Applications
1993 · Peter Pöchmüller, Norbert Wehn, et al. · Kluwer international series in engineering and computer science
High-Level Synthesis mansformat ions for Programmable Architectures
1993 · P. Pochmuller, M. Glesner, et al.
Works count: 28
Citation count: 99
H-index: 5
I10-index: 3
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