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Robert A. Ashton

Observed names: Ashton, R Ashton, R. A. Ashton, R. Ashton, R.A. Ashton, Robert Ashton
OpenAlex ID: A5034840211
Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps
2004 · R. A. Ashton, B. E. Weir, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 32
Standardization of the transmission line pulse (TLP) methodology for electrostatic discharge (ESD)
2003 · Steven H. Voldman, R.A. Ashton, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 29
Electrostatic Discharge
2007 · Robert A. Ashton · Wiley eBooks · 26
A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies
2003 · S. Voldman, W. Anderson, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 25
Modified transmission line pulse system and transistor test structures for the study of ESD
2002 · R.A. Ashton · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 21
Extraction of time dependent data from time domain reflection transmission line pulse measurements [ESD protection design]
2005 · R.A. Ashton · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 15
COM2 SiGe modular BiCMOS technology for digital, mixed-signal, and RF applications
2002 · M. Carroll, T. Ivanov, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Voltages before and after current in HBM testers and real HBM
2005 · Jon Barth, R.A. Ashton, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 13
Modeling and characterization of MOSFET width dependencies
2002 · R.A. Ashton, P.A. Layman, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 13
Gate oxide thickness measurement using Fowler-Nordheim tunneling
2002 · R.A. Ashton · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 12
A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies
2001 · S Voldman, W Anderson, et al. · Microelectronics Reliability · 12
Evaluation of high dose, high energy boron implantation into Cz substrates for epi-replacement in CMOS technology
2001 · K.K. Bourdelle, Yuanning Chen, et al. · IEEE Transactions on Electron Devices · 12
HMM round robin study: What to expect when testing components to the IEC 61000-4-2 waveform
2012 · Kathleen Muhonen, R.A. Ashton, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 10
Characterization of off Chip ESD protection devices
2008 · R.A. Ashton, L. Lescouzères · 10
Pre Pulse Voltage in the Human Body Model
2006 · R.A. Ashton, E. Worley · Electrical Overstress/Electrostatic Discharge Symposium · 10
Transmission line pulse measurements: a tool for developing ESD robust integrated circuits
2004 · R.A. Ashton · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 10
FCDM measurements of small devices
2009 · Martin Johnson, R.A. Ashton, et al. · 9
High-Speed TLP and ESD Characterization of ICs
2021 · Kathleen Muhonen, Evan Grund, et al. · IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) · 8
HBM tester parasitic effects on high pin count devices with multiple power and ground pins
2006 · Chaine, Meuse, et al. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) · 7
Twin tub III - A third generation CMOS technology
1984 · J. Agraz-Guerena, R.A. Ashton, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
A merged 2.5 V and 3.3 V 0.25-μm CMOS technology for ASICs
2002 · I.C. Kizilyalli, R. Huang, et al. · Custom Integrated Circuits Conference · 6
Epi-replacement in CMOS technology by high dose, high energy boron implantation into Cz substrates
2002 · K.K. Bourdelle, Y. Chen, et al. · International Conference on Ion Implantation Technology · 6
VF-TLP round robin study, analysis and results
2008 · Muhonen, Ashton, et al. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) · 4
Electrostatic discharge (ESD) technology benchmarking strategy for evaluating ESD robustness of CMOS technologies
2002 · S. Voldman, W. Anderson, et al. · IEEE International Integrated Reliability Workshop final report · 4
Electrostatic test structures for transmission line pulse and human body model testing at wafer level
2018 · Robert Ashton, Stephen Fairbanks, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 3
Works count: 42
Citation count: 333
H-index: 12
I10-index: 16
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