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Takayuki Uchiyama

The application of SMASH alignment system for 65-55-nm logic devices
2007 · M. Miyasaka, H. Saito, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 18
SMO for 28-nm logic device and beyond: impact of source and mask complexity on lithography performance
2010 · Seiji Nagahara, Kazuyuki Yoshimochi, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 13
Standard wafer with programed defects to evaluate the pattern inspection tools for 300-mm wafer fabrication for 7-nm node and beyond
2019 · Susumu Iida, Takamitsu Nagai, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 12
Study of iso-dense bias (IDB) sensitivity to laser spectral shape at the 45nm node
2007 · Kazuyuki Yoshimochi, Takayuki Uchiyama, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 8
Comparison between optical proximity effect of positive and negative tone patterns in KrF lithography
1997 · Masashi Fujimoto, Takeo Hashimoto, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 8
Fabricating programmed micro-defects on a line and space pattern with an ultra-low line edge roughness <1 nm
2019 · Susumu Iida, Takayuki Uchiyama · Micro and Nano Engineering · 5
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Optimized structure of standard sample with programed defects for pattern inspection using electron beams
2018 · Susumu Iida, Takayuki Uchiyama · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 5
Top coat less resist process development for contact layer of 40nm node logic devices
2010 · Masafumi Fujita, Takayuki Uchiyama, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5
32nm node device laser-bandwidth OPE sensitivity and process matching
2009 · Kazuyuki Yoshimochi, Takao Tamura, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5
45nm node logic device OPE matching between exposure tools through laser bandwidth tuning
2008 · Kazuyuki Yoshimochi, Takao Tamura, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5
Development of standard samples with programmed defects for evaluation of pattern inspection tools for 7-nm and smaller nodes
2019 · Susumu Iida, Takamitsu Nagai, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 4
Development of standard samples with programmed defects for evaluation of pattern inspection tools
2019 · Susumu Iida, Takamitsu Nagai, et al. · Metrology, Inspection, and Process Control XXXVI · 4
Defect Reduction in ArF Immersion Lithography Using Particle Trap Wafers With CVD Thin Films
2009 · Y. Matsui, N. Onoda, et al. · IEEE Transactions on Semiconductor Manufacturing · 3
Focus, dynamics, and defectivity performance at wafer edge in immersion lithography
2008 · Takao Tamura, Naka Onoda, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3
Reticle Critical Dimension Latitude for Fabrication of 0.18 µm Line Patterns
1998 · Seiji Matsuura, Takayuki Uchiyama, et al. · Japanese Journal of Applied Physics · 3
Standing Wave Effect of Various Illumination Methods in 0.25 µm KrF Excimer Laser Lithography
1995 · Takayuki Uchiyama, Satomi Shioiri, et al. · Japanese Journal of Applied Physics · 3
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CD uniformity improvement of through-pitch contact-hole patterning for advanced logic devices
2011 · Takaaki Kuribayashi, Yoshinori Matsui, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2
SMO mask requirements for low k 1 lithography
2010 · Seiji Nagahara, Kazuyoshi Kawahara, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2
Defectivity improvement by modified wafer edge treatment in immersion lithography
2009 · Masafumi Fujita, Takao Tamura, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2
Improvement of gate CD uniformity for 55 nm node logic devices
2008 · Takashi Murakami, Taisaku Nakata, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2
Evaluation of immersion lithography processes for 55-nm node logic devices
2007 · Taisaku Nakata, Teruhiko Kodama, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2
Mask 3D effect reduction and defect printability of etched multilayer EUV mask
2019 · Takashi Kamo, Takeshi Yamane, et al. · Extreme Ultraviolet (EUV) Lithography · 1
Challenges for low-k1 lithography in logic devices by source mask co-optimization
2010 · Kazuyuki Yoshimochi, Seiji Nagahara, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1
Benefit of ArF immersion lithography in 55 nm logic device manufacturing
2007 · Takayuki Uchiyama, Takao Tamura, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1
Reduction of mask error enhancement factor (MEEF) by the optimum exposure dose self-adjusted mask
2001 · Seiji Matsuura, Takayuki Uchiyama, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1
Works count: 35
Citation count: 120
H-index: 5
I10-index: 3
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