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C. Vérove

Observed names: C Verove, C. Verove, Christophe Verove, Christophe Vérove, Verove, C., Vérove, C., Vérove, Christophe
OpenAlex ID: A5075845702
Unbiased line width roughness measurements with critical dimension scanning electron microscopy and critical dimension atomic force microscopy
2012 · L. Azarnouche, E. Pargon, et al. · Journal of Applied Physics · 59
Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning
2012 · Laurent Azarnouche, Erwine Pargon, et al. · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 41
Integration of fluorine-doped silicon oxide in copper pilot line for 0.12-μm technology
2002 · J.P Reynard, C Verove, et al. · Microelectronic Engineering · 30
Residue growth on metallic-hard mask after dielectric etching in fluorocarbon-based plasmas. I. Mechanisms
2010 · N. Posseme, T. Chevolleau, et al. · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 23
Plasma treatments to improve line-width roughness during gate patterning
2013 · Laurent M. Azarnouche, Erwine Pargon, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 18
Integration of a 3 level Cu-SiO/sub 2/ air gap interconnect for sub 0.1 micron CMOS technologies
2001 · V. Arnal, J. Torres, et al. · IEEE International Interconnect Technology Conference (IITC) · 16
Demonstration of an extendable and industrial 300mm BEOL integration for the 65-mn technology node
2005 · O. Hinsinger, R. Fox, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Residue growth on metallic hard mask after dielectric etching in fluorocarbon based plasmas. II. Solutions
2011 · N. Posseme, R. Bouyssou, et al. · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 14
Porous SiOCH Integration: Etch Challenges with a Trench First Metal Hard Mask Approach
2011 · Nicolas Possémé, Thibaut David, et al. · ECS Transactions · 9
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Optimization of CVD dielectric process to achieve reliable ultra low-k air gaps
2002 · Vincent Arnal, Joaquin Torres, et al. · Microelectronic Engineering · 9
Electron-shading characterization in a HDP contact etching process using a patterned CHARM wafer
2002 · J.-P. Carrere, T. Poiroux, et al. · International Symposium on Plasma Process-Induced Damage · 6
Etching process scalability and challenges for ULK materials
2010 · T. Chevolleau, N. Posseme, et al. · IEEE International Interconnect Technology Conference (IITC) · 5
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New etch challenges for the 65-nm technology node Low-k integration using An enhanced Trench First Hard Mask architecture
2006 · N. Posseme, C. Maurice, et al. · IEEE International Interconnect Technology Conference (IITC) · 5
Impact of ambient atmosphere on plasma-damaged porous low-k characterization
2011 · M. Darnon, T. Chevolleau, et al. · IEEE International Interconnect Technology Conference (IITC) · 4
Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions
2011 · Nicolas Posseme, Thibaut David, et al. · ECS Transactions · 4
In situ post etching treatment as a solution to improve defect density for porous low-k integration using metallic hard masks
2009 · N. Posseme, R. Bouyssou, et al. · IEEE International Interconnect Technology Conference (IITC) · 4
Dual damascene architectures evaluation for the 0.18 μm technology and below
2002 · C. Verove, B. Descouts, et al. · IEEE International Interconnect Technology Conference (IITC) · 4
Plasma treatment to improve linewidth roughness during gate patterning
2012 · L. Azarnouche, E. Pargon, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3
Copper dual damascene integration using organic low k material: construction architecture comparison
2002 · Y. Morand, M. Assous, et al. · IEEE International Interconnect Technology Conference (IITC) · 3
Scatterometric Porosimetry for porous low-k patterns characterization
2011 · R. Hurand, R. Bouyssou, et al. · IEEE International Interconnect Technology Conference (IITC) · 2
Comparison between hybrid and porous dielectric material (SiOCH) integration strategies for interconnect technologies
2008 · Ducoté, J., David, T., et al. · HAL · 1
Investigation of Synchronized Pulsed Plasma for High Selective Etching of Silicon Nitride Spacers
2012 · Romuald Blanc, Olivier Joubert, et al. · ECS Meeting Abstracts
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Plasmas Processes Challenges for Porous SiCOH Integration in Advanced Interconnects
2012 · Chevolleau, T., Darnon, Maxime, et al. · HAL
Plasma Etching for Back End Of Line Applications
2012 · Darnon, Maxime, Chevolleau, T., et al. · HAL
Challenges related to linewidth roughness
2012 · Pargon, Erwine, Azarnouch, Laurent, et al. · HAL
Works count: 43
Citation count: 275
H-index: 9
I10-index: 8
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