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Shinsuke Sakashita

Praseodymium silicate formed by postdeposition high-temperature annealing
2004 · Akira Sakai, Shinsuke Sakashita, et al. · Applied Physics Letters · 57
Cost-Effective 28-nm LSTP CMOS using gate-first metal gate/high-k technology
2006 · T. Tomimatsu, Y. Goto, et al. · Symposium on VLSI Technology · 10
Effect of Sintering Atmosphere on Dielectric Properties of LaAlO3-SrTiO3System
2009 · T. Shimada, X. Ziegler, et al. · Ferroelectrics · 5
Diffusion Control Techniques for TiN Stacked Metal Gate Electrodes for p-Type Metal Insulator Semiconductor Field Effect Transistors
2007 · Shinsuke Sakashita, Takaaki Kawahara, et al. · Japanese Journal of Applied Physics · 5
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Enhanced Performance of Gate-First p-Channel Metal–Insulator–Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method
2007 · Naomu Kitano, Shinya Horie, et al. · Japanese Journal of Applied Physics · 4
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Investigation of the Divided Deposition Method of TiN Thin Films for Metal–Insulator–Metal Capacitor Applications
2005 · Tomonori Okudaira, Takeshi Hayashi, et al. · Japanese Journal of Applied Physics · 4
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Application of positron lifetime spectroscopy to the study of material processing of Nd–Fe–B permanent magnets
2009 · T. Nishiuchi, S. Sakashita, et al. · Journal of Magnetism and Magnetic Materials · 3
Phase and Composition Control of Ni Fully Silicided Gates by Nitrogen Ion Implantation and Double Ni Silicidation
2008 · Kazuhiko Yamamoto, Shinsuke Sakashita, et al. · Japanese Journal of Applied Physics · 3
Performance Enhancement in 45-nm Ni Fully-Silicided Gate/High-k CMIS Using Substrate Ion Implantation
2006 · Y. Nishida, T. Yamashita, et al. · Symposium on VLSI Technology · 3
High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method
2007 · Takaaki Kawahara, Yukio Nishida, et al. · ECS Transactions · 2
Advanced Poly-Si NMIS and Poly-Si/TiN PMIS Hybrid-Gate High-k CMIS using PVD/CVD-Stacked TiN and Local Strain Technique
2007 · Y. Nishida, T. Kawahara, et al. · Symposium on VLSI Technology · 2
Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS
2006 · T. Hayashi, Y. Nishida, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Gate Leakage Advantage of LaO Incorporation for Vt Tuning in High-k nMOSFETs over Metal Gate WF Control
2009 · M. Kadoshima, S. Sakashita, et al. · International Conference on Solid State Devices and Materials (SSDM)
ゲートファーストメタルゲート/高k技術を用いたコスト効率的な28nm LSTP CMOS
2009 · T. Tomimatsu, Y. Goto, et al. · Symposium on VLSI Technology
(100)及び(110)Si上に製作したLa含有高k/メタルゲートNMOSFETの閾値電圧低下におけるエリアスケーリングの影響
2009 · M Inoue, Y Satoh, et al. · Symposium on VLSI Technology
Thin-Metal Inserted Single-phase Ni-FUSI(MISF) and High-k Gate Stack for Productive LSTP CMOS Application
2008 · Y. Yamamoto, Y. Nishida, et al. · International Conference on Solid State Devices and Materials (SSDM)
High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method
2007 · Takaaki Kawahara, Yukio Nishida, et al. · ECS Meeting Abstracts
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Reduction of Threshold Voltage by Diffusion Control Technique in p-MISFETs Using Poly-Si/TiN/HfSiON Gate Stacks
2007 · Takaaki Kawahara, Yukio Nishida, et al. · IEEE Electron Device Letters
Low Threshold Voltage Gate-First pMISFETs with Poly-Si/TiN/HfSiON Stacks Fabricated with PVD-based In-situ Solid Phase Interface Reaction (SPIR) Method
2007 · N. Kitano, H. Arimura, et al. · International Conference on Solid State Devices and Materials (SSDM)
Low temperature divided CVD technique for TiN metal gate electrodes of p-MISFETs
2007 · Shinsuke Sakashita, Kenichi Mori, et al. · International Conference on Solid State Devices and Materials (SSDM)
Diffusion control technique in TiN stacked metal gate electrodes for p-MISFETs
2007 · S. Sakashita, T. Kawahara, et al. · International Conference on Solid State Devices and Materials (SSDM)
Phase and Composition Control of Ni-FUSI gates by N2 I/I with Double Ni-silicidation
2007 · K. Yamamoto, S. Sakashita, et al. · International Conference on Solid State Devices and Materials (SSDM)
Impact of area scaling on threshold voltage lowering in La-containing high-k/metal gate NMOSFETs fabricated on (100) and (110)Si
2006 · Masashi Inoue, Yuko Satoh, et al. · Symposium on VLSI Technology
A New Divided Deposition Method of TiN Thin Films for MIM Capacitor Applications
2004 · Shinsuke Sakashita, Takeshi Hayashi, et al. · International Conference on Solid State Devices and Materials (SSDM)
Local electrical properties of HfO/sub 2/ thin films measured by conducting atomic force microscopy
2002 · T. Goto, S. Sakashita, et al. · International Workshop on Gate Insulator (IWGI)
Works count: 25
Citation count: 100
H-index: 4
I10-index: 2
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