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Dong-il Bae

Observed names: D. -I. Bae, D. Bae, D. I. Bae, D.-I. Bae, D.I. Bae, Dong-Il Bae
OpenAlex ID: A5110066438
3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
2018 · Geumjong Bae, D.-I. Bae, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 378
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
2014 · K. -I. Seo, B. Haran, et al. · Symposium on VLSI Technology · 103
Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure
2006 · C.-H. Lee, J. Choi, et al. · Symposium on VLSI Technology · 37
A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond
2016 · Dong-il Bae, Geumjong Bae, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 34
Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB
2016 · Guangfan Jiao, Maria Toledano-Luque, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24
Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
2014 · K. Cheng, S. Seo, et al. · Symposium on VLSI Technology · 19
A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices
2007 · Hyunjin Lee, Seong-Wan Ryu, et al. · Symposium on VLSI Technology · 15
Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations
2005 · Yong-Sung Kim, Eun-Cheol Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12
10nm FINFET technology for low power and high performance applications
2014 · D. Guo, H. Shang, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 10
Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond
2004 · J.W. Lee, Y.S. Kim, et al. · European Solid-State Circuits Conference (ESSCIRC) · 9
Highly manufacturable 90 nm DRAM technology
2003 · Y.K. Park, C.H. Cho, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics
2013 · Bomsoo Kim, Dong-Il Bae, et al. · IEEE Electron Device Letters · 6
Low-Cost and Highly Heat Controllable Capacitorless PiFET (Partially Insulated FET) 1T DRAM for Embedded Memory
2008 · Dong-il Bae, Sungho Kim, et al. · IEEE Transactions on Nanotechnology · 6
Data Retention Time and Electrical Characteristics of Cell Transistor According to STI Materials in 90 nm DRAM
2003 · S. H. Shin, S. H. Lee, et al. · Journal of the Korean Physical Society · 5
Multiple data storage of URAM (Unified-RAM) with multi dual cell (MDC) method
2008 · Dong-il Bae, Bonsang Gu, et al. · IEEE Silicon Nanoelectronics Workshop · 4
Data Retention Time and Electrical Characteristics of Cell Transistor According to STI Materials in 90 ㎚ DRAM
2003 · Sangchul Shin, S.H. Lee, et al. · JSTS Journal of Semiconductor Technology and Science · 3
A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM
2009 · Dong-Il Bae, Seong-Wan Ryu, et al. · Microelectronic Engineering · 2
Retention Mechanism in Double-Gate 1T Capacitorless DRAM by Using PiFET Structure
2007 · Dong-il Bae, Sungho Kim, et al. · IEEE Silicon Nanoelectronics Workshop · 1
Improvement of data retention time using DRAM cell with metallic shield embedded (MSE)-STI for 90nm technology node and beyond
2003 · S.H. Lee, S.H. Hong, et al. · 1
Investigation on high performance 1 transistor capacitorless DRAM with PiFET and ONO structure for embedded memory = Embedded memory를 위한 PiFET과 ONO 구조를 갖는 고성능 1 transistor capacitorless DRAM 연구
2008 · Dong-il Bae, 배동일
A Novel Cell Structure with Bit Line Cap Spacer (BCS) and Top Enlarged Storage Node Contact (TESC) for 90 nm DRAM Technology and Beyond
2004 · C.J. Yun, Y.K. Park, et al. · International Conference on Solid State Devices and Materials (SSDM)
Improvement of metal photo process margin with OPC and CMP for 0.14 μm DRAM technology node and beyond
2001 · Dong-il Bae, Jun-Sik Bae, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Works count: 22
Citation count: 676
H-index: 9
I10-index: 9
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