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David P. Klaus

Observed names: D Klaus, D. Klaus, D. P. Klaus, D.P. Klaus, David Klaus, Klaus, D.
Institution: IBM (United States)
OpenAlex ID: A5110112040
Two-Dimensional Pattern Formation Using Graphoepitaxy of PS‑ b ‑PMMA Block Copolymers for Advanced FinFET Device and Circuit Fabrication
2014 · Hsinyu Tsai, Jed W. Pitera, et al. · ACS Nano · 170
Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
2013 · S. Bangsaruntip, K. Balakrishnan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 108
A high performance liner for copper damascene interconnects
2001 · D. Edelstein, C. Uzoh, et al. · IEEE International Interconnect Technology Conference (IITC) · 97
High performance 0.1 μm CMOS devices with 1.5 V power supply
2002 · Y. Taur, S. Wind, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 94
FinFET performance advantage at 22nm: An AC perspective
2008 · M. Guillorn, J. Chang, et al. · Symposium on VLSI Technology · 86
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
2010 · S. Bangsaruntip, A. Majumdar, et al. · Symposium on VLSI Technology · 65
Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
2008 · H. Kawasaki, M. Khater, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62
Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources
2010 · Zhen Zhang, F Pagette, et al. · IEEE Electron Device Letters · 61
Pattern collapse mitigation strategies for EUV lithography
2012 · Dario L. Goldfarb, Robert L. Bruce, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 41
Resistivity of copper interconnects beyond the 7 nm node
2015 · A. Pyzyna, R. Bruce, et al. · Symposium on VLSI Technology · 32
Low dielectric constant nanocomposite thin films based on silica nanoparticle and organic thermosets
2007 · Qinghuang Lin, Stephen A. Cohen, et al. · Journal of Polymer Science Part B Polymer Physics · 26
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
2004 · D. Edelstein, H. Rathore, et al. · IEEE International Reliability Physics Symposium proceedings · 24
Resistivity of copper interconnects at 28 nm pitch and copper cross-sectional area below 100 nm2
2017 · A. Pyzyna, H. Tsai, et al. · IEEE International Interconnect Technology Conference (IITC) · 20
An ultra-low power 0.1 μm CMOS
2002 · Y. Mii, S. Wind, et al. · Symposium on VLSI Technology · 20
Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
2004 · D. Edelstein, C. Davis, et al. · IEEE International Interconnect Technology Conference (IITC) · 17
Electron-beam lithography for advanced device prototyping: Process tool metrology
1993 · M. G. Rosenfield, M. G. R. Thomson, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 16
High-$\kappa$/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
2010 · Marwan H. Khater, Zhen Zhang, et al. · IEEE Electron Device Letters · 14
Properties Development During Curing of Low Dielectric-Constant Spin-On Glasses
1998 · Robert F. Cook, Eric G. Liniger, et al. · MRS Proceedings · 14
Optimization of SiCOH dielectrics for integration in a 90nm CMOS technology
2004 · A. Grill, D. Edelstein, et al. · IEEE International Interconnect Technology Conference (IITC) · 13
A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar
2003 · G.G. Shahidi, J. Warnock, et al. · Symposium on VLSI Technology · 12
Image processing using shape recognition for alignment to damaged registration marks in electron beam lithography
2009 · E. Kratschmer, D. P. Klaus, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 11
Patterning of CMOS device structures for 40-80nm pitches and beyond
2012 · S. U. Engelmann, R. Martin, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 10
Pattern transfer of directed self-assembly patterns for CMOS device applications
2013 · Hsin-Yu Tsai, Hiroyuki Miyazoe, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 8
A 0.021 µm 2 trigate SRAM cell with aggressively scaled gate and contact pitch
2011 · Michael Guillorn, Josephine Chang, et al. · Symposium on VLSI Technology · 8
Fabrication of compact 100 nm-scale silicon metal–oxide–semiconductor field effect transistors
1992 · S. J. Wind, C. M. Reeves, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 6
Works count: 37
Citation count: 1,064
H-index: 16
I10-index: 22
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