Get started
Author

Fareen Adeni Khaja

Observed names: F. A. Khaja, F. Khaja, F.-A. Khaja, F.A. Khaja, Fareen Khaja, Fareen-Adeni Khaja
OpenAlex ID: A5111007692
Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes
2016 · C.-N. Ni, K.V. Rao, et al. · Symposium on VLSI Technology · 39
Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation
2016 · H. Yu, M. Schaekers, et al. · Symposium on VLSI Technology · 36
Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation
2017 · J-L. Everaert, M. Schaekers, et al. · Symposium on VLSI Technology · 35
Drain current variability and MOSFET parameters correlations in planar FDSOI technology
2011 · J. Mazurier, O. Weber, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 33
Fin Doping by Hot Implant for 14nm FinFET Technology and Beyond
2013 · Bingxi Sun Wood, Fareen Adeni Khaja, et al. · ECS Transactions · 30
Advanced CMOS devices: Challenges and implant solutions
2013 · Benjamin Colombeau, Baonian Guo, et al. · physica status solidi (a) · 28
Comprehensive study of Ga activation in Si, SiGe and Ge with 5 × 10−10Ω·cm2contact resistivity achieved on Ga doped Ge using nanosecond laser activation
2017 · Lin-Lin Wang, Hao Yu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27
Physical understanding of cryogenic implant benefits for electrical junction stability
2012 · Fareen Adeni Khaja, Benjamin Colombeau, et al. · Applied Physics Letters · 24
p-Type MOSFET Contact Resistance Improvement by Conformal Plasma Doping and Nanosecond Laser Annealing
2019 · C. I. Li, N. Breil, et al. · IEEE Electron Device Letters · 13
Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations
2019 · Fareen Adeni Khaja · MRS Advances · 12
PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond
2016 · C.-N. Ni, Y.-C. Huang, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 12
Bulk FinFET junction isolation by heavy species and thermal implants
2014 · Fareen Adeni Khaja, Hans-Joachim L. Gossmann, et al. · International Conference on Ion Implantation Technology · 10
Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length
2012 · C. Xu, P. Batude, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 9
FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)
2012 · B. Sklenard, C. Xu, et al. · Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon · 9
Benefits of Damage Engineering for PMOS Junction Stability
2011 · Fareen Khaja, Benjamin Colombeau, et al. · AIP conference proceedings · 9
Heated implantation with amorphous Carbon CMOS mask for scaled FinFETs
2013 · M. Togo, Y. Sasaki, et al. · Symposium on VLSI Technology · 7
Novel solutions to enable contact resistivity <1E-9 Ω-cm2 for 5nm node and beyond
2018 · Raymond Hung, Hua Chung, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 6
Ultra-low (1.2×10−9 Ωcm2) p-Si0.55Ge0.45 contact resistivity (ρc) using nanosecond laser anneal for 7nm nodes and beyond
2017 · Chih-Yang Chang, Fareen Adeni Khaja, et al. · International Workshop on Junction Technology · 6
NMOS contact resistivity reduction with implants into silicides
2013 · K. V. Rao, Fareen Adeni Khaja, et al. · Physica status solidi. C, Conferences and critical reviews/Physica status solidi. C, Current topics in solid state physics · 4
Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs
2013 · Benoit Sklenard, Perrine Batude, et al. · Solid-State Electronics · 4
NMOS contact resistance reduction with selenium implant into NiPt silicide
2012 · K. V. Rao, F. A. Khaja, et al. · AIP conference proceedings · 4
Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates
2014 · Rinus T.P. Lee, Y. Ohsawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3
Selenium segregation optimization for 10 nm node contact resistivity
2014 · C.-N. Ni, K.V. Rao, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
Schottky barrier height tuning using P+ DSS for NMOS contact resistance reduction
2012 · Fareen Adeni Khaja, K. V. Rao, et al. · AIP conference proceedings · 3
Two-terminal diode steering element for 3D X-bar memory
2012 · Er-Xuan Ping, Y. Erokhin, et al. · International Workshop on Junction Technology · 2
Works count: 33
Citation count: 373
H-index: 11
I10-index: 12
Year
Topic
Type