Author

S. Wada

Observed names: S Wada, S.-I. Wada

Institution: NEC (Japan)

Observed institution: NEC (Japan)

OpenAlex ID: A5111081689

120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

2004 · Y. Suzuki, Z. Yamazaki, et al. · IEEE Journal of Solid-State Circuits · 52

Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology

1990 · Y. Hayashi, S. Wada, et al. · Symposium on VLSI Technology · 26

A new three dimensional IC fabrication technology, stacking thin film DUAL-CMOS layers

1991 · Y. Hayashi, K. Oyama, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 21

40-Gb/s optical receiver IC chipset - including a transimpedance amplifier, a differential amplifier, and a decision circuit - using GaAs-based HBT technology

2003 · Y. Amamiya, Y. Suzuki, et al. · IEEE MTT-S International Microwave Symposium digest · 20

Compensation for PMD-induced time-variant waveform distortions in 43-Gbit/s NRZ transmission by ultra-wideband electrical equalizer module

2006 · S. Wada, R. Ohhira, et al. · Optical Fiber Communication Conference · 15

110Gb/s multiplexing and demultiplexing ICs

2004 · Y. Suzuki, Y. Arnamiya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 14

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

1996 · T. Maeda, K. Numata, et al. · IEEE Journal of Solid-State Circuits · 14

An ultralow-power-consumption, high-speed, GaAs 256/258 dual-modulus prescaler IC

1999 · T. Maeda, S. Wada, et al. · IEEE Journal of Solid-State Circuits · 12

A 27/GHz/151 mW GaAs 256/258 dual-modulus prescaler IC with 0.1 μm double-deck-shaped (DDS) gate E/D-HJFETs

2002 · S. Wada, T. Maeda, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 7

Record highest sensitivity of -28.0 dBm at 10 Gb/s achieved by newly developed extremely-compact superlattice-APD module with TIA-IC

2002 · K. Sato, T. Hosoda, et al. · Optical Fiber Communication Conference · 7

An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance

1999 · S. Wada, J. Yamazaki, et al. · IEEE Transactions on Electron Devices · 6

An ultra-low-power-consumption high-speed GaAs 256/258 dual-modulus prescaler IC

2002 · T. Maeda, S. Wada, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 5

0.2-μm fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

1998 · S. Wada, M. Tokushima, et al. · IEEE Transactions on Electron Devices · 5

A 10 Gb/s optical transmitter module with a built-in modulator driver IC and a receiver module with a built-in preamplifier IC

2003 · N. Yoshida, M. Ishizaka, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 4

Ultra low power consumption heterojunction FET 8:1 MUX/1:8 DEMUX for 2.4 Gbps optical fiber communication systems

2002 · K. Numata, M. Fujii, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 4

A 1.2GHz single-chip NMOS PLL

1985 · T. Yamada, S. Wada, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 4

"A sub-0.25μm symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering"

2005 · S. Wada, M. Tokushima, et al. · Conference digest · 3

A 0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

2002 · S. Wada, J. Yamazaki, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 3

High-speed and simple estimation algorithm of waveform distortions using a 43-Gb/s SiGe-based eye-Monitoring LSI

2008 · N. Yoshida, H. Noguchi, et al. · European Conference on Optical Communication · 2

0.1-μm p/sup +/-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques

1998 · S. Wada, N. Furuhata, et al. · IEEE Transactions on Electron Devices · 2

Volt-ampere-hour meter using a digital signal processor

2003 · M. Komatsu, T. Kobayashi, et al. · IEEE International Symposium on Circuits and Systems proceedings · 1

0.1-μm p/sup +/-GaAs gate HJFETs with f/sub T/=121 GHz fabricated using all dry-etching and selective MOMBE growth

2002 · S. Wada, N. Furuhata, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 1

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's

1998 · M. Fujii, K. Numata, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1

Automatic Fault Tracing Using an E-Beam Tester with Reference to a Good Sample

1997 · S.-I. Wada, T. Nakamura · Proceedings - International Symposium for Testing and Failure Analysis · 1

Silicon device thinning using preferential polishing: progress in flatness and electrical properties

1992 · S Wada, S Takahashi, et al. · Semiconductor Science and Technology · 1

Works count: 34

Citation count: 231

H-index: 8

I10-index: 8