Author

Byron Ho

Observed name: B. Ho

Observed institutions: Motorola (United States), University of California, Berkeley

OpenAlex ID: A5111503389

A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

2017 · C. Auth, A. Aliyarukunju, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 397

Effectiveness of Stressors in Aggressively Scaled FinFETs

2012 · Nuo Xu, Byron Ho, et al. · IEEE Transactions on Electron Devices · 48

Design Optimization of Multigate Bulk MOSFETs

2012 · Byron Ho, Xin Sun, et al. · IEEE Transactions on Electron Devices · 35

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

2012 · Nuo Xu, Byron Ho, et al. · IEEE Electron Device Letters · 30

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

2012 · Nuo Xu, Francois Andrieu, et al. · Symposium on VLSI Technology · 24

Planar GeOI TFET Performance Improvement With Back Biasing

2012 · Peter Matheu, Byron Ho, et al. · IEEE Transactions on Electron Devices · 19

A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications

2002 · A.H. Perera, B. Smith, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 16

Evolutionary MOSFET Structure and Channel Design for Nanoscale CMOS Technology

2012 · Byron Ho · eScholarship (California Digital Library) · 11

PDF

pMOSFET Performance Enhancement With Strained $ \hbox{Si}_{1 - x}\hbox{Ge}_{x}$ Channels

2012 · Byron Ho, Nuo Xu, et al. · IEEE Transactions on Electron Devices · 9

Study of High-Performance Ge pMOSFET Scaling Accounting for Direct Source-to-Drain Tunneling

2011 · Byron Ho, Nuo Xu, et al. · IEEE Transactions on Electron Devices · 9

First Demonstration of Quasi-Planar Segmented-Channel MOSFET Design for Improved Scalability

2012 · Byron Ho, Xin Sun, et al. · IEEE Transactions on Electron Devices · 7

Fabrication of $\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}$ pMOSFETs Using Corrugated Substrates for Improved $I_{\rm ON}$ and Reduced Layout-Width Dependence

2012 · Byron Ho, Nuo Xu, et al. · IEEE Transactions on Electron Devices · 6

Benefits of segmented Si/SiGe p-channel MOSFETs for analog/RF applications

2013 · Nuo Xu, Byron Ho, et al. · Symposium on VLSI Technology · 3

Fabrication of segmented-channel MOSFETs for reduced short-channel effects

2011 · Byron Ho, Xin Sun, et al. · International Semiconductor Device Research Symposium · 3

Electrical Characterization of Etch Rate for Micro- and Nano-Scale Gap Formation

2010 · Donovan Lee, Helen Tran, et al. · Journal of Microelectromechanical Systems · 2

Effectiveness of strained-Si technology for thin-body MOSFETs

2012 · Nuo Xu, Changhwan Shin, et al. · IEEE International SOI Conference (SOI) · 1

Study of Germanium Epitaxial Recrystallization on Bulk-Si Substrates

2010 · Byron Ho, Reinaldo Vega, et al. · MRS Proceedings · 1

Segmented-channel Si1−xGex/Si pMOSFET for improved ION and reduced variability

2012 · Byron Ho, Nuo Xu, et al. · Symposium on VLSI Technology

Epitaxial Growth of Si/Si1-xGex Films on Corrugated Substrates for Improved pMOSFET Performance

2012 · Saurabh Chopra, Vinh Tran, et al. · International Silicon-Germanium Technology and Device Meeting (ISTDM)

Segmented-channel Si1−xGex/Si pMOSFET for improved ION and reduced variability

2012 · Byron Ho, Nuo Xu, et al.

Advanced Nitrogen Preimplant Gate Oxide Technique for Suppression of RNWE and RSCE for 0.18 um CMOS Technology

1999 · Shih-Fen Huang, Helmut Puchner, et al. · European Solid-State Device Research Conference

Works count: 21

Citation count: 621

H-index: 9

I10-index: 8