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Ruilong Xie
Institution:
IBM Research - Albany
Observed institutions:
Agency for Science, Technology and Research,
IBM (United States),
National University of Singapore,
Singapore Science Park,
GlobalFoundries (United States),
Institute of Microelectronics,
IBM Research - Albany
show all 7
OpenAlex ID:
A5111676896
Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond
2018
·
Chi-Chun Liu
, Elliott Franke
, et al.
·
Nature Electronics
·
141
Scaling Challenges for Advanced CMOS Devices
2017
·
Ajey P. Jacob
, Ruilong Xie
, et al.
·
International Journal of High Speed Electronics and Systems
·
141
Effects of Sulfur Passivation on Germanium MOS Capacitors With HfON Gate Dielectric
2007
·
Ruilong Xie
, Chunxiang Zhu
·
IEEE Electron Device Letters
·
74
High-k gate stack on germanium substrate with fluorine incorporation
2008
·
Ruilong Xie
, Mingbin Yu
, et al.
·
Applied Physics Letters
·
70
Interface-Engineered High-Mobility High-$k$/Ge pMOSFETs With 1-nm Equivalent Oxide Thickness
2009
·
Ruilong Xie
, Thanh Hoa Phung
, et al.
·
IEEE Transactions on Electron Devices
·
47
Effects of fluorine incorporation and forming gas annealing on high-k gated germanium metal-oxide-semiconductor with GeO2 surface passivation
2008
·
Ruilong Xie
, Wei He
, et al.
·
Applied Physics Letters
·
45
High mobility high-k/Ge pMOSFETs with 1 nm EOT -New concept on interface engineering and interface characterization
2008
·
Ruilong Xie
, Thanh Hoa Phung
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
41
Backside Power Distribution for Nanosheet Technologies Beyond 2nm
2024
·
Ruilong Xie
, Wonhyuk Hong
, et al.
·
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
·
26
Scaling Challenges for Advanced CMOS Devices
2017
·
Ajey P. Jacob
, Ruilong Xie
, et al.
·
Selected topics in electornics and systems
·
19
Effective Surface Passivation by Novel $\hbox{SiH}_{4}$ –$\hbox{NH}_{3}$ Treatment and BTI Characteristics on Interface-Engineered High-Mobility $\hbox{HfO}_{2}$-Gated Ge pMOSFETs
2010
·
Ruilong Xie
, Thanh Hoa Phung
, et al.
·
IEEE Transactions on Electron Devices
·
18
CMP Challenges for Advanced Technology Nodes
2017
·
John H. Zhang
, Haigou Huang
, et al.
·
MRS Advances
·
14
Energy distribution of interface traps in germanium metal-oxide-semiconductor field effect transistors with HfO2 gate dielectric and its impact on mobility
2008
·
Ruilong Xie
, Nan Wu
, et al.
·
Applied Physics Letters
·
9
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
2019
·
Andrew Greene
, Huimei Zhou
, et al.
·
Symposium on VLSI Technology
·
8
Low Temperature Metal Induced Lateral Crystallization of Ge Using Germanide Forming Metals
2009
·
Thanh Hoa Phung
, Ruilong Xie
, et al.
·
Journal of The Electrochemical Society
·
8
PDF
Palladium-Induced Lateral Crystallization of Amorphous-Germanium Thin Film on Insulating Substrate
2009
·
Ruilong Xie
, Thanh Hoa Phung
, et al.
·
Electrochemical and Solid-State Letters
·
8
PDF
CMP: Consideration of Stop-on Selectivity in Advanced Node Semiconductor Manufacturing Technology
2017
·
Stan Tsai
, Hari Amanapu
, et al.
·
ECS Transactions
·
7
PDF
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
2019
·
Ruilong Xie
, Chanro Park
, et al.
·
Symposium on VLSI Technology
·
6
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
2020
·
Su-Chen Fan
, Ruilong Xie
, et al.
·
IEEE International Interconnect Technology Conference (IITC)
·
4
Interface engineering for high-k/Ge gate stack
2008
·
Ruilong Xie
, Chunxiang Zhu
·
IEEE International Conference on Solid-State and Integrated Circuit Technology
·
2
Gas cluster ion beam processing for improved self aligned contact yield at 7 nm node FinFET: MJ: MOL and junction interfaces
2018
·
Su Chen Fan
, Sean Teehan
, et al.
·
ASMC proceedings
·
1
Low Temperature Metal-Induced Lateral Crystallization of Si1-xGex Using Silicide/Germanide-Forming-Metals
2010
·
Thanh Hoa Phung
, Ruilong Xie
, et al.
·
Japanese Journal of Applied Physics
·
1
PDF
Asymmetric Energy Distribution of Interface Traps in Germanium MOSFETs with HfO2 Gate Dielectric
2008
·
Ruilong Xie
, Nan Wu
, et al.
·
ECS Transactions
·
1
PDF
Enhanced Ge MOS Device Performance Through a Novel Post-gate CF4-plasma Treatment Process
2008
·
Ruilong Xie
, Muruganandam Thamarai
, et al.
·
ECS Transactions
·
1
PDF
Effects of Sulfur Passivation on Ge MOS Capacitors with High-k Gate Dielectric
2007
·
Ruilong Xie
, Chunxiang Zhu
·
International Conference on Solid State Devices and Materials (SSDM)
·
1
Backside Contact Resistivity Reduction for Nanosheet Technologies Beyond 2nm by Backside Nanosecond Laser Anneal Without Impacting the Frontside Cu BEOL
2026
·
Ruilong Xie
, Kevin Brew
, et al.
·
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
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Works count:
31
Citation count:
693
H-index:
11
I10-index:
11
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