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Kang-Ill Seo

Surface Charge Density of Unpassivated and Passivated Metal-Catalyzed Silicon Nanowires
2006 · Kang-ill Seo, Shashank Sharma, et al. · Electrochemical and Solid-State Letters · 124
Improvement in High-$k$$(hboxHfO_2/hboxSiO_2)$Reliability by Incorporation of Fluorine
2006 · K. Seo, R. Sreenivasan, et al. · IEEE Electron Device Letters · 57
Chemical states and electronic structure of a HfO2∕Ge(001) interface
2005 · Kang-Ill Seo, Paul C. McIntyre, et al. · Applied Physics Letters · 51
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Formation of an interfacial Zr-silicate layer between ZrO2 and Si through in situ vacuum annealing
2005 · Kang-ill Seo, Paul C. McIntyre, et al. · Applied Physics Letters · 40
Chemical states and electrical properties of a high-k metal oxide/silicon interface with oxygen-gettering titanium-metal-overlayer
2006 · Kang-Ill Seo, Dong-Ick Lee, et al. · Applied Physics Letters · 39
Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices
2010 · Kwan-Yong Lim, Hyunjung Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 37
A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond
2016 · Dong-il Bae, Geumjong Bae, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 34
Backside Power Distribution for Nanosheet Technologies Beyond 2nm
2024 · Ruilong Xie, Wonhyuk Hong, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 26
Random Telegraph Noise in n-type and p-type silicon nanowire transistors
2008 · Seungwon Yang, Kyoung Hwan Yeo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 21
Fluorine incorporation at HfO2∕SiO2 interfaces in high-k metal-oxide-semiconductor gate stacks: Local electronic structure
2007 · Jeong-Hee Ha, Kang-ill Seo, et al. · Applied Physics Letters · 21
Improvement in high-k (HfO/sub 2//SiO/sub 2/) reliability by incorporation of fluorine
2006 · Kang-ill Seo, R. Sreenivasan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
2024 · Chen Zhang, SeungMin Song, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?
2006 · Paul McIntyre, David Chi, et al. · ECS Transactions · 14
10nm FINFET technology for low power and high performance applications
2014 · D. Guo, H. Shang, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 10
Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics
2013 · Bomsoo Kim, Dong-Il Bae, et al. · IEEE Electron Device Letters · 6
Highly manufacturable 1 Gb NAND flash using 0.12 μm process technology
2002 · Jung-Dal Choi, Seong-Soon Cho, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 5
Next-generation logic design architecture for vertical-transport nanosheets
2023 · Biswanath Senapati, Jeongho Do, et al. · DTCO and Computational Patterning · 1
Integrated simulation of equipment and topography for plasma etching in the DRM reactor
2002 · Won-Young Chung, Jae-Joon Oh, et al. · International Conference on Simulation of Semiconductor Processes and Devices · 1
Backside Contact Resistivity Reduction for Nanosheet Technologies Beyond 2nm by Backside Nanosecond Laser Anneal Without Impacting the Frontside Cu BEOL
2026 · Ruilong Xie, Kevin Brew, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
2025 · N. Lanzillo, J. Mazza, et al. · Technical digest - International Electron Devices Meeting/Technical digest
Predictive Simulations and Experimental Study of AlN Bonding for Better Thermal Dissipation in BSPDN
2025 · Sarabjot Singh, Sangshin Jang, et al. · IEEE International Interconnect Technology Conference (IITC)
5nm論理およびそれ以上の応用のための新しい引張Si(n)と圧縮SiGe(p)二重チャネルCMOS FinFET共積分スキーム【Powered by NICT】
2016 · Bae Dong-il, Bae Geumjong, et al. · IEEE Conference Proceedings
Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?
2006 · Paul McIntyre, David Chi, et al. · ECS Meeting Abstracts
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Characterization, engineering, and reliability of nano-scale high-k dielectrics and semiconductors interfaces
2006 · Kang-Ill Seo
Chemical states and electronic structure of a HfO(-2) / Ge(001) interface
2005 · Kang-ill Seo, Paul C. McIntyre, et al. · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)
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Works count: 25
Citation count: 519
H-index: 13
I10-index: 14
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