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T. Shibata

Observed names: T Shibata, T. SHIBATA, Tadashi Shibata, textscYukio Shibata
Observed institutions: Panasonic (Japan), Toshiba (Japan), Chinese University of Hong Kong, Tohoku University, Hitachi (Japan), The University of Tokyo, Stanford University
OpenAlex ID: A5111934278
A functional MOS transistor featuring gate-level weighted sum and threshold operations
1992 · T. Shibata, T. Ohmi · IEEE Transactions on Electron Devices · 612
Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation
1993 · T. Shibata, T. Ohmi · IEEE Transactions on Electron Devices · 149
Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications
1993 · T. Shibata, T. Ohmi · IEEE Transactions on Electron Devices · 118
An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems
2003 · M. Yagi, T. Shibata · IEEE Transactions on Neural Networks · 103
Formation of device-grade epitaxial silicon films at extremely low temperatures by low-energy bias sputtering
1989 · T. Ohmi, T. Ichikawa, et al. · Journal of Applied Physics · 99
Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment
2002 · K. Kotani, T. Shibata, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 97
An intelligent MOS transistor featuring gate-level weighted sum and threshold operations
2002 · T. Shibata, T. Ohmi · Technical digest - International Electron Devices Meeting/Technical digest · 96
Improvement of threshold voltage deviation in damascene metal gate transistors
2001 · A. Yagishita, T. Saito, et al. · IEEE Transactions on Electron Devices · 77
I n s i t u substrate-surface cleaning for very low temperature silicon epitaxy by low-kinetic-energy particle bombardment
1988 · T. Ohmi, T. Ichikawa, et al. · Applied Physics Letters · 74
A fully parallel vector-quantization processor for real-time motion-picture compression
1999 · A. Nakada, T. Shibata, et al. · IEEE Journal of Solid-State Circuits · 67
A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture
2007 · H. Yamasaki, T. Shibata · IEEE Journal of Solid-State Circuits · 58
Low-temperature silicon epitaxy by low-energy bias sputtering
1988 · T. Ohmi, K. Matsudo, et al. · Applied Physics Letters · 52
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An optimally designed process for submicron MOSFETs
1981 · T. Shibata, K. Hieda, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 50
CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters
1998 · K. Kotani, T. Shibata, et al. · IEEE Journal of Solid-State Circuits · 49
Neuron MOS winner-take-all circuit and its application to associative memory
1993 · T. Yamashita, T. Shibata, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 44
Metal Silicon Reactions Induced by CW Scanned Laser and Electron Beams
1981 · T. Shibata, T. W. Sigmon, et al. · Journal of The Electrochemical Society · 44
Multiple-clue face detection algorithm using edge-based feature vectors
2004 · Y. Suzuki, T. Shibata · IEEE International Conference on Acoustics Speech and Signal Processing · 43
A neuron-MOS neural network using self-learning-compatible synapse circuits
1995 · T. Shibata, H. Kosaka, et al. · IEEE Journal of Solid-State Circuits · 43
Clock-controlled neuron-MOS logic gates
1998 · K. Kotani, T. Shibata, et al. · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 41
Silicide formation using a scanning cw laser beam
1980 · T. Shibata, J. F. Gibbons, et al. · Applied Physics Letters · 38
Real-time reconfigurable logic circuits using neuron MOS transistors
1993 · T. Shibata, K. Kotani, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 37
An optimally designed process for submicrometer MOSFET's
1982 · T. Shibata, K. Hieda, et al. · IEEE Transactions on Electron Devices · 37
An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning Neuron-MOS neural networks
1995 · H. Kosaka, T. Shibata, et al. · IEEE Transactions on Electron Devices · 34
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Robust cephalometric landmark identification using support vector machines
2003 · S. Chakrabartty, M. Yagi, et al. · IEEE International Conference on Acoustics Speech and Signal Processing · 31
A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all
2003 · M. Ogawa, K. Ito, et al. · Symposium on VLSI Circuits · 29
Works count: 146
Citation count: 2,983
H-index: 28
I10-index: 61
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