Author

Kyoung Hwan Yeo

Observed names: Kyoung Yeo, Kyounghawn Yeo

Institutions: Samsung (South Korea), Samsung Electronics (South Korea)

Observed institutions: Korea University, Samsung (South Korea), Samsung Advanced Institute of Technology (South Korea), Samsung Electronics (South Korea)

OpenAlex ID: A5111936031

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

2006 · Sung Dae Suk, Sung-Young Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 235

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

2006 · Kyoung Hwan Yeo, Sung Dae Suk, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 198

Investigation of nanowire size dependency on TSNWFET

2007 · Sung Dae Suk, Ming Li, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 97

Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

2006 · Ming Li, Kyoung Hwan Yeo, et al. · Symposium on VLSI Technology · 71

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

2008 · Sung Dae Suk, Kyoung Hwan Yeo, et al. · IEEE Transactions on Nanotechnology · 55

Sub 30 nm multi-bridge-channel MOSFET(MBCFET) with metal gate electrode for ultra high performance application

2005 · Eun-Jung Yoon, Sung-Young Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 40

Gate-all-around Twin Silicon nanowire SONOS Memory

2007 · Sung Dae Suk, Kyoung Hwan Yeo, et al. · Symposium on VLSI Technology · 31

Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs)

2007 · Keun Hwi Cho, Sung Dae Suk, et al. · IEEE Electron Device Letters · 28

Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process

2006 · Keun Hwi Cho, Sung Dae Suk, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

2005 · Chang Woo Oh, Sung Dae Suk, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28

Characterization and Modeling of 1/$f$ Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

2010 · Rock-Hyun Baek, Chang-Ki Baek, et al. · IEEE Transactions on Nanotechnology · 25

TSNWFET for SRAM cell application: Performance variation and process dependency

2008 · Sung Dae Suk, Yun Young Yeoh, et al. · Symposium on VLSI Technology · 25

A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application

2005 · Sung Min Kim, Eun Jung Yoon, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24

Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

2007 · Ming Li, Kyoung Hwan Yeo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23

Random Telegraph Noise in n-type and p-type silicon nanowire transistors

2008 · Seungwon Yang, Kyoung Hwan Yeo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 21

Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

2013 · Faraz Najam, Yun Seop Yu, et al. · IEEE Transactions on Electron Devices · 20

Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory

2008 · Kyoung Hwan Yeo, Keun Hwi Cho, et al. · Symposium on VLSI Technology · 19

Extracting Mobility Degradation and Total Series Resistance of Cylindrical Gate-All-Around Silicon Nanowire Field-Effect Transistors

2009 · Luryi Choi, Byoung Hak Hong, et al. · IEEE Electron Device Letters · 14

$C$–$V$ Characteristics in Undoped Gate-All-Around Nanowire FET Array

2010 · Rock-Hyun Baek, Chang-Ki Baek, et al. · IEEE Electron Device Letters · 12

Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor

2009 · Yun Young Yeoh, Sung Dae Suk, et al. · IEEE International Reliability Physics Symposium proceedings · 10

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

2010 · Dong-Won Kim, Kyoung Hwan Yeo, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 7

Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

2008 · Dong-Won Kim, Ming Li, et al. · IEEE International SOI Conference (SOI) · 7

Lateral Integration of Partially Insulated and Bulk MOSFETs Using Partial SOI Process

2006 · Sung Hwan Kim, Jeongnam Han, et al. · IEEE International SOI Conference (SOI) · 7

Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions

2004 · Chang Woo Oh, Kyoung Hwan Yeo, et al. · European Solid-State Circuits Conference (ESSCIRC) · 6

80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)

2004 · Kyoung Hwan Yeo, Chang Woo Oh, et al. · Symposium on VLSI Technology · 6

Works count: 38

Citation count: 1,067

H-index: 17

I10-index: 20