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Cécile Aulnette
Observed names:
Aulnette, C.,
C Aulnette,
C. Aulnette,
Cecile Aulnette
Observed institutions:
Soitec (France),
IBM (United States),
Commissariat à l'Énergie Atomique et aux Énergies Alternatives,
Laboratoire d'Électronique des Technologies de l'Information
OpenAlex ID:
A5111989208
Engineering strained silicon on insulator wafers with the Smart CutTM technology
2004
·
B. Ghyselen
, J.-M. Hartmann
, et al.
·
Solid-State Electronics
·
123
Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
2012
·
A. Khakifirooz
, K. Cheng
, et al.
·
Symposium on VLSI Technology
·
42
High-resistivity with PN interface passivation in 22 nm FD-SOI technology for low-loss passives at RF and millimeter-wave frequencies
2023
·
L. Nyssens
, M. Rack
, et al.
·
Solid-State Electronics
·
12
Ultra-Thin Film SOI/BOX Substrate Development, Its Application and Readiness
2011
·
Walter Schwarzenbach
, Xavier Cauchy
, et al.
·
ECS Transactions
·
12
PDF
Impact of substrate resistivity on spiral inductors at mm-wave frequencies
2022
·
Lucas Nyssens
, Martin Rack
, et al.
·
Solid-State Electronics
·
11
Modeling and direct extraction of band offset induced by stress engineering in silicon-on-insulator metal-oxide-semiconductor field effect transistors: Implications for device reliability
2009
·
X. Garros
, F. Rochette
, et al.
·
Journal of Applied Physics
·
11
Highly-Strained Silicon-On-Insulator Development
2006
·
Takeshi Akatsu
, Jean-Michel Hartmann
, et al.
·
ECS Transactions
·
11
PDF
Stress Metrology : The challenge for the next generation of engineered wafers
2004
·
Antoine Tiberj
, Vincent Paillard
, et al.
·
MRS Proceedings
·
10
High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI
2022
·
M. Rack
, L. Nyssens
, et al.
·
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
·
9
Overview of FDSOI technology from substrate to device
2009
·
Bich-Yen Nguyen
, Carlos Mazure
, et al.
·
International Semiconductor Device Research Symposium
·
9
Dual strained channel CMOS in FDSOI architecture: New insights on the device performance
2011
·
C. Le Royer
, M. Cassé
, et al.
·
Solid-State Electronics
·
8
SiGe and Ge on Insulator Wafers
2011
·
Nicolas Daval
, Christophe Figuet
, et al.
·
ECS Transactions
·
5
PDF
Dual channel and strain for CMOS co-integration in FDSOI device architecture
2010
·
C. Le Royer
, M. Casse
, et al.
·
European Solid-State Device Research Conference
·
5
Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H
2008
·
Phuong Nguyen
, K. K. Bourdelle
, et al.
·
Journal of Applied Physics
·
5
PDF
Strain characterization of strained silicon on insulator wafers
2004
·
V Paillard
, B Ghyselen
, et al.
·
Microelectronic Engineering
·
5
PN Junctions Interface Passivation in 22 nm FDSOI for Low-Loss Passives
2022
·
L. Nyssens
, M. Rack
, et al.
·
International Conference on Microwaves, Radar & Wireless Communications
·
4
Ultra Thin silicon substrate for next generation technology nodes
2010
·
W. Schwarzenbach
, Xavier Cauchy
, et al.
·
IEEE International Symposium on Semiconductor Manufacturing conference proceedings
·
4
Ultra-thin SOI for 20nm node and beyond
2011
·
C. Aulnette
, W. Schwarzenbach
, et al.
·
IEEE International SOI Conference (SOI)
·
1
SiGe and Ge on Insulator Wafers
2011
·
Nicolas Daval
, Charlotte Drazek
, et al.
·
ECS Meeting Abstracts
·
1
PDF
Strained Silicon On Insulator wafers made by the Smart Cut™ technology
2004
·
B. Ghyselen
, Y. Bogumilowicz
, et al.
·
MRS Proceedings
·
1
High Ge content Si / SiGe heterostructures for microelectronics and optoelectronics purposes
2004
·
Bogumilowicz, Y.
, Hartmann, J.M.
, et al.
·
HAL
·
1
SSROI (super-steep retrograde on insulator) substrates for RF switch and LNA device performance enhancement
2024
·
Hideki Takeuchi
, Robert J. Stephenson
, et al.
·
IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Ultra-Thin Film SOI/BOX Substrate Development, Its Application and Readiness
2011
·
Walter Schwarzenbach
, Xavier Cauchy
, et al.
·
ECS Meeting Abstracts
PDF
On the Mechanism of the Smart Cut Layer Transfer in Relaxed SiGe Layers
2006
·
Phuong Nguyen
, C. Aulnette
, et al.
·
ECS Meeting Abstracts
PDF
Smart Cut Technology: The Path for Advanced SOI Substrates
2005
·
H. Moriceau
, C. Lagahe-Blanchard
, et al.
·
NATO science series. Series II, Mathematics, physics and chemistry
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Works count:
25
Citation count:
290
H-index:
9
I10-index:
8
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