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Len Tsou

Observed names: L. Tsou, L. Y. TSOU, L. Y. Tsou
Institution: IBM (United States)
OpenAlex ID: A5113497219
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
2005 · E. Leobandung, H. Nayakama, et al. · Symposium on VLSI Technology · 63
A high performance 90nm SOI technology with 0.992 μm/sup 2/ 6T-SRAM cell
2003 · M. Khare, S.H. Ku, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 43
A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
2002 · P. Smeys, V. McGahay, et al. · Symposium on VLSI Technology · 24
Highly Selective Reactive Ion Etching of Polysilicon with Hydrogen Bromide
1989 · L. Y. Tsou · Journal of The Electrochemical Society · 20
Reactive Ion Etching of Indium Tin Oxide with Hydrogen Bromide
1993 · L. Y. Tsou · Journal of The Electrochemical Society · 14
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32 nm logic patterning options with immersion lithography
2008 · K. Lai, S. Burns, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 12
TDMOS-an ultra-low on-resistance power transistor
1988 · S. Mukherjee, M. Kim, et al. · IEEE Transactions on Electron Devices · 11
A high current power IC technology using trench DMOS power device
2002 · S. Mukherjee, M. Kim, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Effect of Photoresist on Plasma Etching
1989 · L. Y. Tsou · Journal of The Electrochemical Society · 6
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Double exposure double etch for dense SRAM: a designer's dream
2008 · Chandrasekhar Sarma, Allen Gabor, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4
Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic
2004 · W.C. Natzle, D. Horak, et al. · ASMC proceedings · 4
Ion Beam‐Assisted Etching of Aluminum with Chlorine
1985 · L. Y. Tsou · Journal of The Electrochemical Society · 4
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Meeting critical gate linewidth control needs at the 65 nm node
2006 · Arpan Mahorowala, Scott Halle, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3
High Pressure Reactive Ion Etching of P-Doped Polysilicon with HCl
1986 · L. Y. Tsou · Japanese Journal of Applied Physics · 2
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A new method for post-etch OPC modeling to compensate for underlayer effects from integrated wafers
2009 · Chandra Sarma, Amr Abdo, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Double exposure double etch for dense SRAM: A designer's dream - art. no. 692429
2008 · Chandra Sarma, Allen H. Gabor, et al.
TEFET-a high density, low erase voltage, trench flash EEPROM
2002 · Di-Son Kuo, M. Simpson, et al. · Symposium on VLSI Technology
Characterization of linewidth variation on 248- and 193-nm exposure tools
2001 · Allen H. Gabor, Timothy A. Brunner, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Stacked oxide as trench gate dielectric
1992 · L. Y. Tsou, D. S. Kuo, et al. · Journal of Vacuum Science & Technology A Vacuum Surfaces and Films
High Rate And Selective Reactive Ion Etching Of Polysilicon
1990 · L. Y. Tsou · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
ChemInform Abstract: Highly Selective Reactive Ion Etching of Polysilicon with Hydrogen Bromide.
1990 · L. Y. TSOU · ChemInform
Works count: 21
Citation count: 217
H-index: 7
I10-index: 7
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