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M. Narihiro

Observed names: Mitsuru Narihiro, Mitsuru Narihiro Mitsuru Narihiro
OpenAlex ID: A5113630003
Low-power embedded ReRAM technology for IoT applications
2015 · M. Ueki, K. Takeuchi, et al. · Symposium on VLSI Technology · 70
Sub-10-nm planar-bulk-CMOS devices using lateral junction control
2004 · H. Wakabayashi, S. Yamagami, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 65
Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control
2006 · H. Wakabayashi, T. Ezaki, et al. · IEEE Transactions on Electron Devices · 39
45-nm gate length CMOS technology and beyond using steep halo
2002 · H. Wakabayashi, M. Ueki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 39
Sub-50-nm physical gate length CMOS technology and beyond using steep halo
2002 · H. Wakabayashi, M. Ueki, et al. · IEEE Transactions on Electron Devices · 38
Low-power embedded ReRAM technology for IoT applications
2015 · M. Ueki, K. T. Akeuchi, et al. · Symposium on VLSI Circuits · 35
Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches
2012 · K. Kaneko, H. Sunamura, et al. · Symposium on VLSI Technology · 18
High-voltage complementary BEOL-FETs on Cu interconnects using N-type IGZO and P-type SnO dual oxide semiconductor channels
2013 · H. Sunamura, K. Kaneko, et al. · Symposium on VLSI Technology · 15
Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films
2007 · Munehiro Tada, Hiroto Ohtake, et al. · IEEE Transactions on Electron Devices · 13
Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners
2006 · M. Tada, T. Tamura, et al. · IEEE Transactions on Electron Devices · 13
Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs
2004 · M. Ueki, M. Narihiro, et al. · Symposium on VLSI Technology · 11
Performance of new E-beam lithography system JBX-9300FS
2000 · H. Takemura, H. Ohki, et al. · Microelectronic Engineering · 11
High on/off-ratio P-type oxide-based transistors integrated onto Cu-interconnects for on-chip high/low voltage-bridging BEOL-CMOS I/Os
2012 · H. Sunamura, K. Kaneko, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
Stabilizing Schemes for the Minority Failure Bits in Ta 2 O 5 -Based ReRAM Macro
2017 · Makoto Ueki, Yoshihiro Hayashi, et al. · IEEE Transactions on Electron Devices · 9
Pushing Planar Bulk CMOSFET Scaling to its Limit by Ultimately Shallow Diffusion-Less Junction
2007 · K. Uejima, K. Yako, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)
2004 · M. Tada, Y. Harada, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
Estimation of Optimum Electron-Beam Projection Lithography Mask Biases Taking Coulomb Beam Blur into Consideration
2003 · Hideo Kobinata, Yasuhisa Yamada, et al. · Japanese Journal of Applied Physics · 9
Interfacial Atomic Structure Between Pt-Added NiSi and Si(001)
2011 · Nobuyuki Ikarashi, Mitsuru Narihiro, et al. · Japanese Journal of Applied Physics · 8
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Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles
2009 · Yoshihiro Hayashi, Mari Abe, et al. · IEEE Transactions on Electron Devices · 7
High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices
2006 · M. Tagami, H. Ohtake, et al. · Symposium on VLSI Technology · 7
Enhanced drivability of high-Vbd dual-oxide-based complementary BEOL-FETs for compact on-chip pre-driver applications
2014 · H. Sunamura, N. Inoue, et al. · Symposium on VLSI Technology · 6
Plasma Co-polymerization Technology with Molecular-level Structure Tightening in "In-situ" SiOCH Stacks for 32nm-node Cu Interconnects
2006 · M. Tada, H. Yamamoto, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects
2005 · M. Tada, H. Ohtake, et al. · Symposium on VLSI Technology · 6
10-nm-Scale Pattern Delineation Using Calixarene Electron Beam Resist for Complementary Metal Oxide Semiconductor Gate Etching
2005 · Mitsuru Narihiro, Kohichi Arai, et al. · Japanese Journal of Applied Physics · 5
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A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI
1999 · H. Wakabayashi, T. Yamamoto, et al. · Symposium on VLSI Technology · 5
Works count: 44
Citation count: 482
H-index: 11
I10-index: 13
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