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S. Kadomura

Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding
2016 · Y. Kagawa, N. Fujii, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 247
Radiation Damage of SiO 2 Surface Induced by Vacuum Ultraviolet Photons of High-Density Plasma
1994 · Tetsuya Tatsumi, Seiichi Fukuda Seiichi Fukuda, et al. · Japanese Journal of Applied Physics · 91
An Advanced CuCu Hybrid Bonding For Novel Stacked CMOS Image Sensor
2018 · Y. Kagawa, N. Fujii, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · 52
The Scaling of Cu-Cu Hybrid Bonding For High Density 3D Chip Stacking
2019 · Y. Kagawa, S. Hida, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · 38
Etch Rate Acceleration of SiO2 during Wet Treatment after Gate Etching
1993 · Tetsuya Tatsumi, Seiichi Fukuda Seiichi Fukuda, et al. · Japanese Journal of Applied Physics · 29
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Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process
2007 · J. Wang, Y. Tateshita, et al. · Symposium on VLSI Technology · 28
Impact of film structure on damage to low-kSiOCH film during plasma exposure
2009 · Shigeo Yasuhara, Juhyun Chung, et al. · Journal of Physics D Applied Physics · 25
High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates
2006 · Y. Tateshita, J. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24
Structure-designable method to form super low-kSiOC film (k= 2.2) by neutral-beam-enhanced chemical vapour deposition
2009 · Shigeo Yasuhara, Juhyun Chung, et al. · Journal of Physics D Applied Physics · 21
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Super-low-k SiOCH film (k = 1.9) with extremely high water resistance and thermal stability formed by neutral-beam-enhanced CVD
2010 · Shigeo Yasuhara, Toru Sasaki, et al. · Journal of Physics D Applied Physics · 18
Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates
2007 · S. Mayuzumi, J. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM
2004 · A. Kajita, T. Usui, et al. · IEEE International Interconnect Technology Conference (IITC) · 14
A 0.11 μm CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores
2002 · Y. Takao, H. Kudo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 14
Three-dimensional structures for high saturation signals and crosstalk suppression in 1.20 μm pixel back-illuminated CMOS image sensor
2013 · T. Shinohara, K. Watanabe, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 13
Atmospheric In situ Arsenic-Doped SiGe Selective Epitaxial Growth for Raised-Extension N-type Metal–Oxide–Semiconductor Field-Effect Transistor
2007 · Tetsuya Ikuta, Yuki Miyanami, et al. · Japanese Journal of Applied Physics · 12
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Mechanism of Carrier Mobility Degradation Induced by Crystallization of HfO2Gate Dielectrics
2009 · Takashi Ando, Takayoshi Shimura, et al. · Applied Physics Express · 11
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On-wafer monitoring of charge accumulation and sidewall conductivity in high-aspect-ratio contact holes during SiO2 etching process
2007 · Butsurin Jinnai, Toshiyuki Orita, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 11
A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide
2003 · A. Suzuki, K. Tabuchi, et al. · Symposium on VLSI Technology · 11
Application of HfSiON to Deep-Trench Capacitors of Sub-45-nm-Node Embedded Dynamic Random-Access Memory
2006 · Takashi Ando, Naoyuki Sato, et al. · Japanese Journal of Applied Physics · 10
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Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond
2005 · H. Miyajima, K. Watanabe, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
High performance copper and low-k interconnect technology fully compatible to 90nm-node SOC application (CMOS4)
2003 · M. Inohara, I. Tamura, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
Characteristics of in-situ phosphorus-doped silicon selective epitaxial growth at atmospheric pressure
2008 · Tetsuya Ikuta, Shigeru Fujita, et al. · Journal of Crystal Growth · 9
High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology
2006 · S. Yamaguchi, K. Tai, et al. · Symposium on VLSI Technology · 9
Breakthrough Integration of 32nm-node CulCntra Low-k SiOC (k=2.0) Interconnects by using Advanced Pore-Sealing and Low-k Hard Mask Technologies
2006 · S. Arakawa, I. Mizuno, et al. · IEEE International Interconnect Technology Conference (IITC) · 9
Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM
2004 · R. Kanamura, Y. Ohoka, et al. · Symposium on VLSI Technology · 9
Works count: 69
Citation count: 828
H-index: 13
I10-index: 21
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